Unlock instant, AI-driven research and patent intelligence for your innovation.

Multi-chip build up package structure for optronic chip and its manufacturing method

A technology for optoelectronic chips and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., and can solve problems such as configuration limitations of conductive lines, long conductive paths, and inability to perform image processing quickly.

Inactive Publication Date: 2007-08-29
ADVANCED SEMICON ENG INC
View PDF0 Cites 16 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the optoelectronic chip packaging structure 100 described above, the optoelectronic chip 120 is a digital signal processor chip (not shown) that is electrically conductive to an external circuit board through the bonding wires 130 and the substrate 110. The path is too long to perform image processing quickly and it is easy to cause cross-talk effect (cross-talk effect)
[0004] Taiwan Patent Certificate No. M246808 "Build-Up Structure of Image Sensor" discloses that an image sensor packaging structure includes a circuit build-up structure, and the image sensing chip is housed in a crystal cavity of a carrier board and senses region facing upward, the circuit build-up structure is formed on the carrier board and on the image sensing chip, since the circuit build-up structure is formed on the active surface of the image sensing chip and the carrier board, when increasing It is easy to contaminate the sensing area of ​​the image sensor chip during the layer packaging process, and the circuit build-up structure must have a window, which cannot cover the sensing area, so the conductive circuit configuration in the circuit build-up structure restricted, unable to densify
In addition, the circuit build-up structure needs to reserve the window, which increases the manufacturing cost

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multi-chip build up package structure for optronic chip and its manufacturing method
  • Multi-chip build up package structure for optronic chip and its manufacturing method
  • Multi-chip build up package structure for optronic chip and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] Please refer to FIG. 2 , a multi-chip build-up packaging structure 200 for optoelectronic chips mainly includes a metal carrier 210, an integrated circuit chip 220, a build-up packaging structure 230 including at least two dielectric layers and at least one circuit layer, an optoelectronic chip 240, and a light-transmitting conductive substrate 250 . In this embodiment, the metal carrier 210 is a copper foil and is patterned. Before patterning, the build-up packaging structure 230 is formed on the metal carrier 210. The build-up packaging structure 230 includes at least The first dielectric layer 231, the first circuit layer 232, the second dielectric layer 233, several conductive components 234 located on the second dielectric layer 233, the third dielectric layer 235, the second circuit layer 236, the fourth The dielectric layer 237 and the third circuit layer 238 are formed on the metal carrier 210 in a build-up manner. Wherein, the materials of the first dielectric...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention relates to a layer-increasing package structure of multiple photoelectric chips including a metal carrier, an IC chip, a photoelectric chip, several dielectric layers and several circuit layers and a transmission conduction base board of a layer-increasing package structure, in which, said IC chip is set on the metal carrier and covered by a dielectric layer, several electrodes of which are connected to the circuit layers, part of said photoelectric chip is embedded in a dielectric layer and exposes a photoelectric action region and several electrodes of the chip, said transmission conduction base board is set above the dielectric layers and the photoelectric chip, and the photoelectric chip and the IC chip embedded in the way of layer-increasing are connected by the circuit layers.

Description

technical field [0001] The invention relates to the packaging technology of optoelectronic chips, in particular to a multi-chip build-up packaging structure of optoelectronic chips and a manufacturing method thereof. Background technique [0002] Optoelectronic chips are used in video electronic products to achieve various functions such as image sensing, image display, lighting, light storage, light output or light input. Due to the large package size of conventional optoelectronic chips, it will occupy the assembly space of video electronic products, and its electrical transmission path is also quite long, which is prone to cross-talk effects. [0003] Please refer to FIG. 1 , a photoelectric chip package structure 100 of a conventional image sensor is a single-chip package type, mainly including a substrate 110 , a photoelectric chip 120 , several bonding wires 130 and a light-transmitting sheet 140 . The substrate 110 has an upper surface 111 and a lower surface 112, wh...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00H01L25/18H01L25/16H01L23/488H01L21/60
CPCH01L24/19H01L2224/48091H01L2224/73265H01L2224/48227H01L2224/32225H01L2224/04105H01L2224/19H01L2224/32245H01L2224/73267H01L2224/92244H01L2924/14H01L2924/3025H01L2924/00014H01L2924/00H01L2924/00012
Inventor 王建皓
Owner ADVANCED SEMICON ENG INC