Multi-chip build up package structure for optronic chip and its manufacturing method
A technology for optoelectronic chips and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., and can solve problems such as configuration limitations of conductive lines, long conductive paths, and inability to perform image processing quickly.
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[0033] Please refer to FIG. 2 , a multi-chip build-up packaging structure 200 for optoelectronic chips mainly includes a metal carrier 210, an integrated circuit chip 220, a build-up packaging structure 230 including at least two dielectric layers and at least one circuit layer, an optoelectronic chip 240, and a light-transmitting conductive substrate 250 . In this embodiment, the metal carrier 210 is a copper foil and is patterned. Before patterning, the build-up packaging structure 230 is formed on the metal carrier 210. The build-up packaging structure 230 includes at least The first dielectric layer 231, the first circuit layer 232, the second dielectric layer 233, several conductive components 234 located on the second dielectric layer 233, the third dielectric layer 235, the second circuit layer 236, the fourth The dielectric layer 237 and the third circuit layer 238 are formed on the metal carrier 210 in a build-up manner. Wherein, the materials of the first dielectric...
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