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Phase detector

A phase detector, trigger technology, applied in the direction of the instrument, the phase angle between the voltage and the current, the measuring device, etc., can solve the problem of the wrong output signal and so on

Inactive Publication Date: 2007-10-03
QIMONDA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A race condition between two input signals passing through a phase detector can lead to a false output signal when the phase difference between the two input signals is small

Method used

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Embodiment Construction

[0011] FIG. 1 is a block diagram illustrating one embodiment of an electronic system 100 . The electronic system 100 includes a host 102 and a storage circuit 106 . Host 102 is electrically coupled to memory circuitry 106 through memory communication path 104 . Host 102 is any suitable electronic host, such as a computer system including a microprocessor or microcontroller. Storage circuit 106 is any suitable memory, such as a memory that operates using a clock signal. In one embodiment, memory circuitry 106 includes random access memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate synchronous dynamic random access memory (DDR-SDRAM) .

[0012] Storage circuit 106 includes phase detector 108 that receives the FB signal on feedback (FB) signal path 110 and the CLK signal on clock (CLK) signal path 112 . In one embodiment, phase detector 108 receives an external clock signal on CLK signal path 112 through...

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Abstract

A phase detector includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a first signal in response to a feedback signal and a clock signal. The second circuit is configured to provide a second signal in response to the clock signal and an inverted clock signal. The third circuit is configured to provide a third signal indicating whether the clock signal leads the feedback signal and a fourth signal indicating whether the feedback signal leads the clock signal in response to the first signal and the second signal.

Description

technical field [0001] The present invention relates to phase detectors. Background technique [0002] Phase detectors are used in a variety of circuits, such as delay-locked loops (DLLs), duty cycle correctors, and other circuits where the phase between two signals is used to adjust a portion of the circuit. Phase detectors are commonly used in memories such as Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Double Data Rate SDRM (DDR-SDRAM). [0003] One type of phase detector receives two input signals and provides two output signals. The phase detector estimates the phase difference between two input signals to provide two output signals. If the first input signal leads the second input signal, the phase detector activates the first output signal and deasserts the second output signal. If the first input signal lags the second input signal, the phase detector activates the second output signal and ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R25/00
CPCH03K5/26H03L7/089
Inventor A·明佐尼
Owner QIMONDA