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Adiabatic cmos design

A C25 and C26 technology, applied in the direction of electrical components, power reduction of field effect transistors, logic circuits, etc., can solve problems such as high loss, change of CMOS block and module design topology layout, etc., and achieve the effect of solving heat and battery-related problems

Inactive Publication Date: 2007-10-17
NXP BV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0015] In both cases, however, the design topology of the CMOS blocks and modules has changed significantly, and the resulting losses are often still too high

Method used

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Experimental program
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Embodiment Construction

[0036] Referring to Figure 4, the well-known concept of variable threshold CMOS is shown whereby the supply voltage applied to the circuit is variable between an active mode and a standby mode in which the active logic circuit is connected between Vdd' and Vss ' rails, and in standby mode connect the circuit to the Vdd and Vss rails. A high threshold voltage (high Vt) transistor (not shown) is placed in series between the corresponding supply rail and the CMOS block (at A and B) to switch between the two modes and to turn on or off The functional cell voltage is turned on, and the purpose of this type of configuration is to try to minimize the functional cell voltage in order to minimize the power consumption, which is achieved by series transistor banks in impedance mode. However, power consumption is also a function of the charge consumption of the power cells, and as stated above, the object of the present invention is to reduce the charge loss in CMOS integrated circuits i...

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Abstract

An integrated circuit comprises a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one of the modules (10) and the first reference line (Vdd) and a second transistor (52) is provided between one of the modules (10) and the second reference line (Vss) and capacitors (C25, C26) are provided in parallel with the transistors (52, 54) such that they are driven as current sources (I1, 12). As a result power dissipation and leakage current is reduced.

Description

technical field [0001] The present invention relates generally to adiabatic CMOS design, and more particularly to CMOS circuit design for reducing leakage current and power dissipation. Background technique [0002] CMOS (complementary metal-oxide-semiconductor) logic uses a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computer, telecommunications, and signal processing equipment. The main advantage of CMOS circuits is that they ideally do not allow current to flow except when the input to the logic gate is switched, and thus dissipate no power. CMOS does this by compensating each n-type MOSFET with a p-type MOSFET, and wiring the same input into two in such a way that if one MOSFET is conducting, the other is not. [0003] MOSFETs have been continuously scaled down over time, firstly because smaller MOSFETs (with shorter channels) allow more current to pass (per sq...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/00
CPCH03K19/0013Y10T29/49002H03K19/00
Inventor 马特·科伦
Owner NXP BV