Multiply adding up device

A technology of multiply-accumulate and add units, which is applied in the field of multiply-accumulate devices, can solve problems such as being difficult to keep up with the operating frequency of DSP, and achieve the effects of satisfying the limitation of bit width, reducing time delay, and reasonable structure arrangement

Inactive Publication Date: 2007-12-05
ZHEJIANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Because modern digital signal processing applications require higher and higher operating frequencies of digital signal processors (DSP), and the circuit delay of MAC is limited by specific physical properties and functional complexity, even with the continuous improvement of semiconductor t

Method used

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Embodiment Construction

[0042] The present invention can be illustrated in detail by the following drawings and descriptions thereof.

[0043] Detailed Description:

[0044] figure 1:

[0045] Multi-bit data A, B H , B L , one bit of data sign_A, sign_B, po_ng, acm_en, shift_en, round_en is the output of the operand decoding unit module 10.

[0046] multi-bit data p * 0 ,p * 4 ,p ** 0 ,p ** 4 , sub_carry * [3:0], sub_carry ** [3:0], one bit data sub_carry * [4], sub_carry ** [4] Generates the output of the cell module 20 for the partial product.

[0047] Multi-bit data sum* 、carry * 、sum ** 、carry ** is the output of the Wallace tree addition unit module 30.

[0048] The multi-bit data mux_product and acm_product are outputs of the accumulation unit module 40 .

[0049] The multi-bit data product is the output of the final result unit module 50

[0050] figure 2:

[0051] For the high half Wallace tree addition logic:

[0052] The specific bit of the partial product of Pxy, whe...

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Abstract

The invention discloses a multiplication accumulation device of multiple multiplication accumulating patterns in the modern digital signal processor, which comprises the following parts: operand decoding unit, partial product generating unit, Wallace tree-typed addition unit, accumulation unit and final result unit, wherein the predecoding unit, partial product generating unit, Wallace tree-typed addition unit, accumulation unit and final result unit are connected sequently. The invention modifies the BOOTH coded algorism to affirm the precision of system, which reduces the time delay of entire MAC.

Description

technical field [0001] The invention relates to a multiply-accumulate device for solving multiple multiply-accumulate modes in modern digital signal processors. Background technique [0002] Multiply-accumulate (MAC) is one of the most common operations in digital signal processing, and there are many modes of multiply-accumulate operations. According to whether the multiplier and the multiplicand are signed numbers, it can be divided into signed number multiply-accumulate and unsigned number multiply-accumulate and mixed signs (one multiplier is a signed number, the other is an unsigned number) multiplication and accumulation, in addition, in some occasions, it is necessary to consider rounding the results of the multiplication and accumulation operation to maintain the accuracy of the calculation, so this brings Here comes how to design a MAC device to meet the requirements of every possible situation. [0003] Because modern digital signal processing applications require...

Claims

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Application Information

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IPC IPC(8): G06F7/533
Inventor 刘鹏范佑夏冰洁姚庆栋
Owner ZHEJIANG UNIV
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