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Semiconductor package and its manufacturing method

A semiconductor and packaging technology, applied in the field of semiconductor packaging and its manufacturing method, can solve the problems of restricting the use of electronic products, being unable to provide electronic products with electrical functions, and providing

Inactive Publication Date: 2007-12-19
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in the above-mentioned various semiconductor packages or the applied CCM package structure, the carrier (such as the substrate or the lead frame) of the semiconductor package or the package structure can only provide electrical contacts electrically connected to the outside below, It is impossible to provide additional electrical contacts on the side of the package or the package structure, or on the upper surface (encapsulation gel part), which will not only fail to provide good electrical functions for electronic products, but will also limit the use of electronic products, such as the inability to carry out packaging. Stacking or inability to use sockets to electrically connect packages to external devices

Method used

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  • Semiconductor package and its manufacturing method
  • Semiconductor package and its manufacturing method
  • Semiconductor package and its manufacturing method

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Embodiment 1

[0024] 1A to 1H are schematic diagrams of Embodiment 1 of the semiconductor package and its manufacturing method of the present invention.

[0025] As shown in Figure 1A, at first, provide a chip carrier module sheet with a plurality of chip carriers, each chip carrier is provided with a plurality of electrical connection points, refer to Figure 1B at the same time, it is the chip carrier module sheet corresponding to Figure 1A The cross-sectional schematic diagram, in this embodiment, the chip carrier module is a substrate module 100, each of the chip carriers is a thin ball grid array (TFBGA) or land grid array (LGA) substrate 10, each of the substrate 10 Divided by a plurality of transverse and vertical cutting lines (as shown by dotted lines), at the same time at the transverse and vertical cutting lines, electroplating bus lines 11 are formed on the upper and lower surfaces of the corresponding substrate module sheet 100, so that the electroplating bus lines 11 The ring i...

Embodiment 2

[0033] 2A to 2E are schematic diagrams of Embodiment 2 of the semiconductor package and its manufacturing method of the present invention. This embodiment is substantially the same as the above embodiment, so the same components will not be described again.

[0034] As shown in FIG. 2A , first provide a substrate module sheet 200 with a plurality of substrates 20, each of the substrates 20 is provided with an electroplating bus 21 between the upper and lower surfaces, and the electroplating bus 21 is extended and electrically connected to the substrate. The surface circuit structure of the sheet 20, wherein a plurality of electrical connection points such as first electrical connection pads 201 and second electrical connection pads 202 are provided on the upper surface of each of the substrates 20, and on the upper surface of the substrate 20 The lower surface is provided with a third electrical connection pad 203, the first electrical connection pad 201 can be electrically con...

Embodiment 3

[0040] FIG. 3 is a schematic diagram of a substrate module used in Embodiment 3 of the semiconductor package and its manufacturing method of the present invention.

[0041] As shown in the figure, this embodiment is substantially the same as the above-mentioned embodiment, the main difference is that the substrate module sheet 300 has a plurality of substrates 30, and the upper and lower surfaces of each substrate 30 are provided with an electroplating bus 31, and The upper surface of each of the substrates 30 is provided with a plurality of electrical connection points such as first electrical connection pads 301 and second electrical connection pads 302, wherein the second electrical connection pads 302 between the adjacent substrates 30 connected together, and the first and second electrical connection pads 301 , 302 are electrically connected to the electroplating bus 31 .

[0042] Subsequent methods such as the above-mentioned embodiments can be used to connect and electr...

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Abstract

This invention discloses a semiconductor package piece and its manufacturing method, in which the piece includes: a chip carrier set with multiple electric connection points, at least one semiconductor chip set and connected to the carrier, multiple conducting pieces set and connected to the connecting points and a package colloid formed on the carrier to cover the chip and the conducting pieces and expose at the side surfaces of the conducting pieces, which can provide extra multiple electric connection points so as to strengthen electric functions of electronic products.

Description

technical field [0001] The present invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package capable of providing additional electrical contacts and its manufacturing method. Background technique [0002] Due to the substantial growth of various portable products such as communication, network and computer, ball grid array (BGA) package, which can reduce the area of ​​integrated circuit (IC) and has high density and multi-pin characteristics, has gradually become the packaging market. It is the mainstream of the Internet, and is often matched with high-performance chips such as microprocessors, chipsets, and graphics chips to perform higher-speed computing functions. Among them, ball grid array (BGA) is an advanced semiconductor chip packaging technology, which is characterized in that a semiconductor chip is placed on a substrate, and a plurality of solder balls (Solder Ball) arranged in a grid array are arranged on ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/60H01L23/498H01L23/31
CPCH01L24/97H01L2224/97H01L2224/73265H01L2224/48227H01L2224/32225H01L24/73H01L2924/14
Inventor 张正易黄建屏黄致明林介源萧承旭
Owner SILICONWARE PRECISION IND CO LTD
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