Low-voltage differential signal receiver

Abstract

This device consists of two differential receivers, two super samplers, the phase-locked circuit, the clock impulse (CI) and the data margin test logic module (MTL). This invention treats the CI signal as another data signal and transfers the CI signal and the data signal via the same circuit layout path. It uses the asynchronous CI to raise the sampling frequency against input IC and data. Then it uses special IC and data MTL to verify the conversion of IC and analyzes out the data byte from the IC and data specimen. This device can effectively raise the transferring efficiency and quality of pixel.

Description

Technical field [0001] The present invention is a low -voltage signal receiving device, especially a low -voltage differential signal receiving device that can improve the quality and efficiency of the transmission of low -voltage difference (LVDS). Background technique [0002] In recent years, due to the faster and faster operation of the processor, the amount of data processing of the unit time has also increased. Therefore, the transmission of the data of computer peripheral equipment and the application of various integrated circuit products.These must be completed by an interface circuit that can be transmitted and received in large quantities.In terms of long -distance transmission of tens of kilometers or even hundreds of kilometers, optical fiber can be used as a transmission tool, but the transmission of flow fiber transmission on each tens of meters or even the circuit board, and the fiber transmission is unrealistic.Therefore, the transmission lines must be relying on...

AI Technical Summary

Problems solved by technology

[0009] The problem with current low voltage differential signaling (LVDS) receivers is that the delay time of each clock and data signal path is different due to many factors. The number, type and manufacturing process of electronic components on each path, voltage variation Factors such as these will cause different timing differences between the corresponding clock pulses and data of each group, which will easily cause sampling errors and affect the quality of signal transmission. It will become more obvious as the pixel transmission rate increases.

[0010] In order to overcome the large number of sampling errors that accompany the increase in pixel transmission rate, under the current low-voltage differential signal (LVDS) receiver architecture, it is necessary to address the number, type, manufacturing process, and voltage of electronic components with different clock pulses and data paths. Changes and other factors make corresponding adjustments in the circuit layout to take into account both the improvement of the pixel transmission rate and the quality of signal transmission. However, this requires a lot of time and effort for the manufacturer.

[0011] Therefore, under the low-voltage differential signal (LVDS) receiver architecture of the prior art, it will be very difficult to increase the pixel transmission rate and take into account the signal transmission quality.

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