A method and device for collection and interweaving of mixed automatic retransfer request
A hybrid automatic retransmission, bit technology, applied in correct operation testing, error correction/detection using interleaving technology, error correction/error detection by combining multiple code structures, etc., can solve the problem of increasing circuit area and wasting logic. resources and other issues, to achieve the effect of reducing area, reducing storage resources, and optimizing processing speed
Inactive Publication Date: 2008-01-16
SANECHIPS TECH CO LTD
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[0024] 2) There are many possibilities for the order in which bits are collected and written into the cache. If the existing possibilities are classified one by one, it will waste logic resources and increase the circuit area
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[0056] The specific embodiments of the method and device of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0057] In the method and device for HARQ bit collection and interleaving of the present invention, the device for HARQ bit collection and interleaving in the HSDPA system is composed of the following parts, as shown in Figure 5, wherein the device includes a pre-bit collection FIFO buffer unit 501, bit collection control unit 502, physical channel interleaving and output control unit 503, the FIFO buffer unit 501 before bit collection includes systematic bit FIFO, check 1 bit FIFO and check 2 bit FIFO.
[0058] The present invention is used for the HARQ bit collection of HSDPA system and the method for interleaving, as shown in Figure 6, it comprises the following steps:
[0059] Step 601: the process starts;
[0060] Step 602: After the second rate matching, the system bit stream, check 1 bit stream, and check 2 ...
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The invention discloses a hybrid automatic repeat request bit collecting and interleaving method and a means. The means thereof comprise a bit collecting fore-FIFO buffer unit, which comprises a system bit FIFO, a check (1) bit FIFO and a check (2) bit FIFO; and a bit collecting control unit, a physical channel interleaving and output control unit, wherein the bit collecting fore-FIFO buffer unit is applied to match the difference between the forestage rate matching and the processing speed of bit collecting and interleaving; the bit collecting control unit is applied for controlling to read out the corresponding column data; the physical channel interleaving and output control unit is applied to obtain the address of each bit in the final physical channel flow by transforming channel flow addresses processed by bit collecting. The method and means in the invention utilize three FIFO buffer structures, which reduces the storage resources of circuit, and reduces the corresponding logical resources by using the combination simplifying the HARQ bit collection write-in order.
Description
technical field [0001] The present invention relates to a third-generation mobile communication system and its method, in particular to a method for collecting and interleaving HARQ bits for high-speed downlink packet access in a wideband code division multiple access system (WCDMA) and device. Background technique [0002] Wideband CDMA (WCDMA) is one of the mainstream systems of the third generation (3G) mobile communication system. Among them, the HSDPA (High Speed Downlink Packet Access, High Speed Downlink Packet Access) technology proposed in the R5 version has become a current research hotspot. HSDPA technology is the most important technology to improve the high-speed downlink data transmission rate of WCDMA network. It is proposed by 3GPP in the R5 protocol in order to meet the asymmetrical requirements of uplink and downlink data services. It can be used without changing the existing WCDMA system network structure. On the basis of this, the user's downlink da...
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IPC IPC(8): H04L1/18H04L1/24H03M13/27H03M13/29
Inventor 王志宇
Owner SANECHIPS TECH CO LTD