Device isolation structure used for high pressure manufacturing process and its manufacturing method

Abstract

The present invention discloses an element isolation structure for high voltage process, which comprises a semiconductor substrate provided with a low voltage zone and a high voltage zone, a STI isolation structure etched on the low voltage zone through light and a LOCOS isolation structure etched on the high voltage zone through light. The present invention also discloses technique and method to produce the element isolation structure, which minimizes module area occupied by the isolation structure based on the same isolation effect of elements.

Description

technical field [0001] The invention relates to a semiconductor device structure, in particular to a device structure for shallow trench isolation mixed local silicon oxidation isolation for high pressure process. The invention also relates to a manufacturing method of the device isolation structure. Background technique [0002] In the manufacturing process of modern semiconductor devices, shallow trench isolation (STI) and local oxide isolation of silicon (LOCOS) are two device isolation structures commonly used. LOCOS has a good isolation effect, but occupies a larger area than STI. With the continuous development of semiconductor device manufacturing technology, the device size is continuously reduced, and the requirements for the area occupied by the device isolation structure are strengthened. Due to its relatively small area, STI has become the mainstream device isolation structure used in advanced manufacturing processes. However, due to the characteristics of its...

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Problems solved by technology

This also leads to many difficulties in the realization of the STI process in the high-pressure process, which is not conducive to the final process control

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