Method for implementing main clock phase alignment and device thereof

A clock phase and phase alignment technology, applied in the field of communication, can solve problems such as poor reliability, phase transient, and system instability, and achieve the effect of ensuring stability

Active Publication Date: 2008-02-27
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a method and device for realizing the phase alignment of the main and standby clocks, which is used to solve the problem that the output clock signals of t

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  • Method for implementing main clock phase alignment and device thereof
  • Method for implementing main clock phase alignment and device thereof
  • Method for implementing main clock phase alignment and device thereof

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Embodiment Construction

[0044] The technical solutions of the present invention will be further described in more detail in conjunction with the accompanying drawings and specific embodiments.

[0045] As shown in FIG. 1 , it is a schematic diagram of the phase-locked loop involved in the present invention, and FIG. 2 is a schematic diagram of the phase alignment of master and standby clocks in the present invention.

[0046] In the communication system, each network element node is equipped with the same two clock units as active and standby. To realize clock master-standby switchover without errors, it must be ensured that the clock signals output by the master and standby clock units are the same at the instant of clock master-standby switchover. In order to provide a continuous and stable clock signal output to each service board, each service board will not generate bit errors due to clock master-standby switchover. To this end, the synchronization of the output signals of the two clock units mu...

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Abstract

This invention discloses a method and a device for aligning phases of master and standby clocks, in which, the method includes: 1, setting a first master phase-locked loop and a first sub-phase-locked loop for the master clock and setting a second master phase-locked loop and a sub-phase-locked loop for the standby clock unit, 2, the master one controls a first clock signal to follow and lock the primary clock signal by opening the first sub-phase-locked loop and closing the first master loop, 3, the standby clock unit aligns the phases of the first and second clock signals by opening the second master loop and closing the second sub-loop and 4, the standby one reads the control value of the second-sub-loop following the first clock signal and controls that the phase of signals is the same when switching the master and sub-phase-locked loops according to the control value.

Description

technical field [0001] The present invention relates to clock synchronization technology in the field of communication technology, in particular to a method and device for phase alignment of active and standby clocks during active and standby clock switching. Background technique [0002] In the synchronous digital communication network, the clock is a very important component, so the backup working mode is adopted in the design of communication equipment, that is, there are two clock units in one network element node, and the two clocks are mutually active and standby. Under normal circumstances, the master clock unit provides timing synchronization signals for communication equipment. Once the master clock unit fails or is artificially switched, the standby clock unit immediately replaces the master clock to provide timing synchronization signals for communication devices. It is necessary to ensure that the business will not be affected when the main and standby clocks are...

Claims

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Application Information

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IPC IPC(8): H04J3/06H04B1/74
Inventor 刘明勇
Owner ZTE CORP
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