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On-site programmable gate array duplex selector verification method

A technology of multiplexer and verification method, applied in the direction of instrument, digital circuit test, electronic circuit test, etc., can solve the problem of not considering whether there is interference in other data paths, and achieve the effect of improving test efficiency and speed

Active Publication Date: 2008-03-05
UNIV OF ELECTRONICS SCI & TECH OF CHINA +1
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AI Technical Summary

Problems solved by technology

[0003] The traditional method of verifying the multiplexer generally only conducts logical analysis on one of the channels to determine whether the data is strobed, but this method does not consider whether there is interference in other data paths, so it is very likely that the gated data will actually be output is the other way

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  • On-site programmable gate array duplex selector verification method
  • On-site programmable gate array duplex selector verification method

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Embodiment Construction

[0017] The present invention closes untested other multiplexers during the testing process. For the multiplexer to be tested, under the condition of fully considering the influence of other data paths, the data path that has not been selected is applied to the opposite direction. The incentive is verified by judging the result, that is, whether it is the data of the selected channel. details as follows.

[0018] See Figure 1.

[0019] The function of the multiplexer is to select several channels of data, and the output expression is shown in (1-1). The test principle of all multiplexers is the same, here we take the 2-input multiplexer as an example to introduce its test theory. The units in the FPGA form a certain function through configuration. As shown in Table 1, each configuration of CMUX can only select one input (V1 / V2) to turn on the output T, as shown by the black path in Figure 1(a). Show. The four-input CMUX has at least four test configurations. The fault model...

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Abstract

The method comprises: 1)in software, sequencing the many-way selector under test, and setting the testing vector and its corresponding true result; saving them; 2) the software automatically generate configuration file based on the test vector of the many-way selector, and sends it to the FPGA to make configuration; the hardware turns off the many-way selector being not under test according to the configuration file, and keeps the many-way selector under test; 3) the software applies the test vector on the hardware FPGA, and returns the result to the software side; the software analyzes the comparison result; 4) selecting the next tested many-way selector, so on unit all tests are completed; 5) completing the test result.

Description

technical field [0001] The invention relates to integrated circuit technology, in particular to field programmable gate array verification technology. Background technique [0002] A multiplexer is one of the commonly used combinational logic components. It uses combinational logic circuits to control digital signals to complete more complex logic functions. It has several data input terminals D0, D1, ..., several control input terminals A0, A1, ..., and an output terminal Y0. By adding appropriate signals to the control input, the desired data signal can be selected from multiple input data sources and sent to the output. When in use, a set of binary coded program signals can also be added to the control input to make the circuit output a series of signals as required, so it is also a programmable logic component. [0003] The traditional method of verifying the multiplexer generally only conducts logic analysis on one of the channels to determine whether the data is str...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317G01R31/3185H03K19/173
Inventor 李威李文昌李平廖永波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA