Method of reducing message transmission overhead of parallel multi-digital signal processor

A digital signal and message transmission technology, applied in the direction of transmission system, baseband system components, electrical components, etc., can solve the problems of reducing communication overhead, receiving data, etc., to reduce burden, good practice effect, shorten communication effect of overhead

Inactive Publication Date: 2008-04-16
BEIHANG UNIV
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  • Abstract
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Problems solved by technology

[0007] However, the current zero-copy technology often uses DMA and memory remapping to realize zero-copy of data packets between the user buffer and the core buffer. The application is closely integrated, and it cannot be regarded as zero copy in the true sense, and there is still potential to be tapped
In addition, in the prior art, the data is not directly taken out from the memory where it is located and sent out through the communication interface, nor is the received data directly put into the destination memory, and a copy is still required. If this copy process can be removed, further Reduce communication overhead

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  • Method of reducing message transmission overhead of parallel multi-digital signal processor
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Embodiment Construction

[0027] The present invention is to solve the problem that in a multi-DSP system, DSPs communicate through high-speed LINK ports, and the communication delay between DSPs is required to be as low as possible. It is proposed due to the requirement of external memory. In order to meet this technical requirement, the method described in the present invention is based on zero-copy technology.

[0028] Zero-copy technology can reduce the communication overhead of traditional operating systems, reduce protocol levels and the number of copies between protocols, and effectively improve communication performance. It mainly includes the following two aspects:

[0029] (1) Create an effective user-level communication interface and eliminate unnecessary copying processes in the system kernel.

[0030] (2) Direct data transmission from the router's input to output, that is, the received message is only buffered once in the memory, and the message in the buffer queue is directly transmitte...

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Abstract

The invention discloses a method for decreasing the spending of information transfer between paralleled multi-digital signal processors; wherein, the data receiving and transmitting between each digital signal processor are realized by LINK port; before transmitting data, the digital signal processor in the transmitter transmits a control frame to make clear the length and the type and so on for the transmitted data firstly; the digital signal processor in the receiver sets the relative receiving address and the length of the receiving data according the type and the length of the received frame; and then the digital signal processor in the transmitter transmits the actual data frame, in this way, the data can be transmitted to the destination directly without needing double buffer. So the invention not only can save the storage room, but also can save the time for copying data. The invention can realize information zero-copy communication in deed by DMA and the relative break treatment program, which can decrease the burden for DSP core in the most degree, shorten the communication spending greatly and obtain a much better practice effect.

Description

technical field [0001] The invention relates to a method capable of reducing message passing overhead among multiple digital signal processors (abbreviated as DSPs) in a loosely coupled parallel processing system based on a message passing mechanism, and belongs to the technical field of signal processing and communication. Background technique [0002] At present, DSP is being widely used in the field of signal processing, especially in image signal processing. However, as the processing capability requirements for signal processing boards are getting higher and higher, for example, the real-time processing of high-frame number and large-size image sequences often requires billions of calculations per second. Currently, the single-chip DSP It is impossible to meet its requirements for computing power, which requires the signal processing board to adopt a multi-DSP parallel processing structure in the design to meet the system's requirements for computing power. [0003] In...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/02H04L25/02
Inventor 李波葛宝珊姜宏旭
Owner BEIHANG UNIV
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