4-end transistor substrate resistance network model

Abstract

The invention relates to a network model for a four-terminal transistor substrate resistance, belonging to the integrated circuit field, which comprises a Rjun.s used to characterize a parasitic resistance between the source electrode and the substrate, a Rjun.d used to characterize a parasitic resistance between the drain electrode and the substrate, two resistances Rbulk and Rwell used to characterize a bulk resistance and a well resistance of the transistor. The four resistances, Rjun.s, Rjun.d, Rbulk and Rwell are connected at a point so as to form a T-shaped network structure of four resistances to characterize a parasitic resistance induced by the substrate. The value of each resistance in the resistance network is changeable according to the transistor size. The substrate resistance network is applicable for various layout type MOS transistors and the JFET junction field-effect transistor, and can ensure the high accuracy of the model in a large size range. The invention has the advantages that the model with variable size is of clear physics significance; the network can be applied in the radio frequency MOS transistor, and ensure the accuracy of the model under the frequency as high as 50GHZ.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a four-terminal transistor substrate resistance network model. Background technique [0002] With the increasing application of CMOS technology in the radio frequency (RF) field, the accuracy of high frequency models of MOS devices is becoming more and more important for RF product design. Since the parasitic effects of MOS devices are more complex at high frequencies and have a greater correlation with the layout, the current practice is to build high-frequency models for MOS devices in the form of macro models. [0003] BSIM3 SPICE model, as the industry standard of CMOS model, has significant deficiencies in simulation and RF performance alone, and its model structure does not include gate resistors and substrate resistor networks. Therefore, the MOS transistor radio frequency circuit simulation macromodel combined with the compact model and the gate resistance, interjuncti...

AI Technical Summary

Problems solved by technology

At present, the "∏" type three-resistor network configuration method is currently widely used, and the specific structure is shown in Figure 1. This model mainly includes MOSFET 1' and three resistors R 1 , R 2 , R 3 and two junction capacitances C SB 、C DB The substrate network 2' constituted can be used at frequencies exceeding 10 GHz, but for applications with higher frequencies, its performance is still not ideal.

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