A forward error compensation and correction method and device for streamline analog/digital converter

An analog-to-digital converter and forward error technology, applied in the direction of analog/digital conversion calibration/testing, can solve problems such as limited application prospects, increase sampling frequency, solve bottlenecks in ADC resolution and speed, and be easy to expand Effect

Inactive Publication Date: 2008-06-04
PEKING UNIV
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Problems solved by technology

Since such methods do not fundamentally solve the problems of po

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  • A forward error compensation and correction method and device for streamline analog/digital converter
  • A forward error compensation and correction method and device for streamline analog/digital converter
  • A forward error compensation and correction method and device for streamline analog/digital converter

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[0034] The present invention will be described in detail below through embodiments and in conjunction with the accompanying drawings.

[0035] As shown in Figures 3 and 4, the present invention proposes a new error correction method for pipeline ADC - forward error compensation. The basic principle is as follows: when the sample and hold circuit in the pipeline stage is in the hold stage, the The voltage error is reflected on the input virtual point 6 of the operational amplifier 4 .

[0036] The following method can approximately deduce the voltage value of the virtual point 6 . During the sampling phase, the total charge of the input is:

[0037] Q S =(C F +C S )×VIN

[0038] C F : Holding capacitor of sub-pipeline stage

[0039] C S : Sampling capacitor of sub-pipeline stage

[0040] During the hold phase, the total charge input is:

[0041] Q h =C F (A×VX+VX)+C S VX

[0042] Desirable C for 1-bit or 1.5-bit pipelining S =C F , the voltage value of the virtu...

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Abstract

The invention relates to a method and a device for forward error compensation and emendation of a pipeline A/D converter. The invention is characterized in that the principle of the forward error compensation and emendation method is as follows: when the sample and hold circuit in the sub-pipeline grade stays in the hold phase, the voltage error of the output point is then reflected to the input virtual location of operational amplifier; the voltage error of the operational amplifier input virtual location of the sub-pipeline grade at a higher level is retained and passed through a forward error compensation circuit and then is compared and calculated with input voltage of the sub-pipeline grade at a lower level; and thus the output voltage error of the sub-pipeline grade at a higher level is accurately compensated to ensure that forward error compensation sample and hold circuit and the pipelining grade use the same clock signal. By adopting the forward error compensation method for the pipeline ADC supported by technologies related to multi-channel and time overlapping, the invention reduces pressure on base-band in the communication receiving system. Similarly, the bottleneck of ADC resolution and speed of software radio engineering in military facilities is solved as well.

Description

technical field [0001] The invention relates to an error correction method for a pipelined analog-to-digital converter, in particular to a forward error compensation correction method and device for a pipelined analog-to-digital converter. Background technique [0002] With the development of electronic technology and computer technology, the use of digital signal systems to process analog signals has become more and more common. But in real life, most signals exist in the form of analog quantities. In the real world, the analog quantity in the form of an electrical signal converted by a sensor needs to be converted into a digital signal through an analog-to-digital converter (ADC) before it can be input into a digital system for processing and control. Therefore, the interface circuit ADC that converts analog quantities into digital quantities is a bridge between analog signals and digital signals, and is also the focus and bottleneck of electronic technology development. ...

Claims

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Application Information

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IPC IPC(8): H03M1/10
Inventor 樊亮李琛廖怀林黄如王阳元
Owner PEKING UNIV
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