Semiconductor memory device
A storage device and semiconductor technology, applied in semiconductor devices, information storage, static memory, etc., can solve problems such as the influence of read bit line potential, power consumption by changes, misreading, etc., and achieve the effect of reducing the cumbersome design and adjustment.
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Embodiment approach 1
[0142] The memory cell provided in the semiconductor memory device of Embodiment 1 has, for example, figure 1 The circuit configuration shown.
[0143] This memory cell 130, called a 2x8 transistor element, has p-channel transistors 106, 107 (PMOS transistors), N-channel transistors 108, 109 (NMOS transistors), write access transistors 116, 117, read drive transistors 120 . Read out the access transistor 122 .
[0144] P-channel transistor 106 and N-channel transistor 108, and P-channel transistor 107 and N-channel transistor 109 constitute a CMOS inverter, respectively.
[0145] The input and output terminals of these CMOS inverters are connected to each other to form a storage circuit 103 (filp-flop circuit).
[0146] The write access transistors 116, 117, when the write language line 110 (WWL) becomes "H (High Level)", make the respective pair of write bit lines 112, 113 (NWBL, WBL) and the storage circuit 103 conductive as Access to the transfer gate.
[0147] In additi...
Embodiment approach 2
[0173] As Embodiment 2 of the present invention, a semiconductor memory device having a hierarchical bit line structure, such as Figure 7 As shown, a semiconductor memory device in which one global read bit line 137 is provided for a plurality of columns (for example, four columns).
[0174] In this semiconductor memory device, the power consumption required for charging and discharging the global read bit lines 137 is only required for one column, regardless of whether any column is the target of read.
[0175] Hereinafter, it demonstrates in more detail.
[0176] In this semiconductor memory device, for example, a plurality of memory cell groups 131 (local blocks) including a plurality of (for example, 16) memory cells 130 described in the first embodiment are provided as a set.
[0177] The above-mentioned memory cell group 131 is arranged in the direction of the global readout bit line 137 to form a column, and four columns are arranged in the direction of the language l...
Embodiment approach 3
[0213] Instead of the local amplifier 136 of Embodiment 2 described above, set as Figure 17 The local amplifier 146 shown is also possible.
[0214] In the local amplifier 146, there is provided a NOR circuit 147 for driving the N-channel transistor N2 by inputting the signal of the local read bit line 114' and the column selection signal NCAD10-11.
[0215] In the case of such a configuration, only the signal corresponding to the data stored in the memory cell 130 of the column selected by the column selection signal is transmitted to one global read bit line 137, that is, while power consumption can be reduced, a wiring area can be obtained. The reduction also becomes easier.
[0216] Also, in the case of using the local amplifier 146 as described above, it is also possible to provide the global read bit line 137 for each column.
[0217] Even in this case, the potential of the global read bit line 137 of the column not selected by the column selection signal is not shift...
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