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Chip packaging structure and method of manufacture

A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of easy shaking, increased packaging cost, electrical short circuit of bonding wires 130, etc.

Inactive Publication Date: 2010-09-08
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in order to allow the chip 120 to be smoothly disposed on the chip holder 112 and electrically connected to these internal pins 114, different types of chips 120 must be matched with different lead frames 110, so the lead frame 110 needs to be changed depending on the size of the chip 120. also specifications, thus increasing package cost
In addition, if a chip 120 with a smaller size is encountered, in order to shorten the length of these bonding wires 130, the adjacent inner pins 114 must extend toward the direction close to the chip 120 to increase the length of these inner pins 114, However, as the distance between these adjacent inner pins 114 shrinks, these inner pins 114 are more likely to shake during the process of forming the colloid 140 , so these adjacent welding wires 130 are prone to electrical short circuits.

Method used

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  • Chip packaging structure and method of manufacture
  • Chip packaging structure and method of manufacture
  • Chip packaging structure and method of manufacture

Examples

Experimental program
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no. 1 example

[0060] 2A is a schematic top view of a chip packaging structure according to the first embodiment of the present invention, and FIG. 2B is a schematic cross-sectional view of the chip packaging structure of FIG. 2A along line I-I'. 2A and 2B, the chip packaging structure 200 of the first embodiment includes a metal layer 210, a thin film circuit layer 220, a chip 230, a plurality of first bonding wires 240, a pin array 250 and a glue 260 . Wherein, the thin film circuit layer 220 is disposed on the metal layer 210 , and the thin film circuit layer 220 includes an insulating film 222 and a circuit layer 224 . The insulating film 222 is disposed on the metal layer 210, and the circuit layer 224 is disposed on the insulating film 222, wherein the circuit layer 224 has a plurality of conductive traces 224a.

[0061] The chip 230 is disposed above the metal layer 210 , and the first bonding wires 240 are electrically connected to the bonding pads 232 of the chip 230 and the conduc...

no. 2 example

[0074] Please refer to FIG. 4 , which is a schematic cross-sectional view of a chip packaging structure according to a second embodiment of the present invention. The main difference between the chip packaging structure 300 of the second embodiment and the chip packaging structure 200 of the first embodiment is that the lead array 350 of the chip packaging structure 300 can be disposed on the thin film circuit layer 320 . In detail, in the second embodiment, the chip packaging structure 300 further includes a conductive layer 390, such as solder, anisotropic conductive paste (ACP), anisotropic conductive film (anisotropic conductive film, ACF) or conductive B stage (B stage) glue. The conductive layer 390 is disposed between one end of the pins 352 and the thin film circuit layer 320 , and at least some of the pins 352 are electrically connected to the conductive traces 324 a through the conductive layer 390 . In other words, in the second embodiment, at least some of the pin...

no. 3 example

[0076] Please refer to FIG. 5 , which is a schematic cross-sectional view of a chip packaging structure according to a third embodiment of the present invention. The main difference between the chip packaging structure 400 of the third embodiment and the chip packaging structures 200 and 300 of the above-mentioned embodiments is that the chip 430 of the chip packaging structure 400 can be disposed on the insulating film 422 of the thin film circuit layer 420 . In addition, the metal layer 410 in this embodiment can be a metal plate as described in the first embodiment, and the metal layer 410 can also be formed on the insulating film 422 by a sputtering process, so that the wiring layer 424 and the metal layer 410 They are respectively located on two opposite surfaces of the insulating film 422 . The metal layer 410 formed by the sputtering process is a metal film thinner than the metal plate.

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Abstract

The invention relates to an encapsulation structure of a chip, which comprises a metal layer, a film line layer, a chip, a pin array and a colloid. The film line layer arranged on metal layer comprises an insulation film which is arranged on the metal layer and a line layer which is arranged on the insulation film. The line layer is provided with a plurality of conductive traces. The chip is arranged upon the metal layer and electrically connected with the conductive traces. The pin array is arranged outside the chip; the pin array has a plurality of pins and at least part of the pins are electrically connected with the conductive traces. The colloid at least covers the chip, the film line layer, part of the pins and part of the metal layer. So same pin array can match with different kinds and different sizes chips.

Description

technical field [0001] The invention relates to a semiconductor element and a manufacturing method thereof, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) can be mainly divided into three stages: IC design, IC process, and IC package. [0003] In the fabrication of integrated circuits, chips are completed through wafer fabrication, integrated circuit formation, and wafer sawing. The wafer has an active surface, which generally refers to the surface of the wafer with active elements. After the integrated circuit inside the wafer is completed, the active surface of the wafer is also equipped with a plurality of bonding pads, so that the chips formed by dicing the wafer can be electrically connected to the outside through these pads. carrier. The carrier is, for example, a leadframe or a package substrate. The chip can be connected to the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/31H01L21/50H01L21/60H01L21/56
CPCH01L2224/92247H01L2224/48091H01L2224/16225H01L2924/19107
Inventor 潘玉堂刘孟学周世文
Owner CHIPMOS TECH INC