Multi-chip semiconductor packaging structure and encapsulation method

Abstract

The invention relates to a method for encapsulating multi-chip semiconductor, which comprises the following steps: a lead frame and at least two chips are provided; the lead frame comprises a tube core pad and a lead arranged around the tube core pad; a through-hole is arranged on the tube core pad and positioned on the edge of the tube core pad; a relative surface of the basement in a first chip is stuck to the tube core pad; the first chip is electrically connected with the lead through the through-hole; the basement surface of a second chip is stuck to the tube core pad; the second chip is arranged on the relative surface with the first chip in the tube core pad; the second chip is electrically connected with the lead; the rest chips are piled upon the first chip and the second chip and electrically connected with the lead; at least two chips are encapsulated to be a type with the lead frame. Through the steps, the invention simplifies the encapsulation process of multi-chip, promotes the thickness of the encapsulation circuit, meanwhile reduces the manufacturing cost and enhances the performance of the circuit operation.

Description

technical field [0001] The invention relates to a multi-chip semiconductor package structure and a package method, in particular to a semiconductor package structure and a package method in which a plurality of chips are connected to each other through a lead frame. Background technique [0002] As the demand for miniaturization, light weight and multi-functionalization of electronic components increases day by day, the packaging density of semiconductors increases continuously. Therefore, it is necessary to reduce the size of the package and the area occupied by the package. Among the technologies developed to meet the above requirements, the multi-chip semiconductor packaging technology makes a profound contribution to the overall cost, performance and reliability of packaged chips. [0003] Existing multi-chip semiconductor package manufacturing method is described as the technical scheme disclosed by the U.S. Patent No. US6674173 as the patent number, and comprises the f...

AI Technical Summary

Problems solved by technology

[0006] In the prior art, chips are bonded on both sides of a single-layer lead frame with an adhesive to form a multi-chip semiconductor package. Since the types of chips on both sides of the lead frame are the same, but the placement directions are different, the internal wiring of the chips on both sides is asymmetrical. , it is necessary to carry out further wiring processing on the chip on one side, so that the pads on the chip on both sides of the lead frame are mirror-symmetrical, which increases the complexity of the chip packaging process and thus increases the cost.

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