12results about How to "Simple packaging process" patented technology

The utility model discloses a kind of metal intelligent chip card packaging structures, including card base and chip module connected on card base, the card base at least includes upper structural layer, antenna layer and lower structural layer which are thin sheet and are sequentially laminated, the antenna layer is equipped with radio frequency antenna, the radio frequency antenna has at least two conductive contact parts, the card base is equipped with the mounting groove for accommodating chip module in the upper of conductive contact part, the mounting groove groove bottom is equipped with the conductive connection groove extending to conductive contact part downwards, the chip module bottom has the chip contact exposed after packaging, the conductive connection groove is equipped with the conductive material column in the lower part and conductive contact part conductive connection, upper part protrudes upwards and is connected with chip contact conductive connection, the utility model aims at overcoming the deficiency of prior art, provide a kind of metal intelligent chip card packaging structure with compact structure, strong stability.

A ceramic substrate power device package comprises a power transistor wafer, a drain electrode bonding pad is arranged on the bottom surface of the power transistor wafer, and a source electrode bonding pad and a switch control electrode bonding pad are arranged on the top surface of the power transistor wafer; the circuit board further comprises a ceramic substrate for bearing a wafer, the ceramic substrate comprises a top circuit layer and a ceramic substrate layer, the top circuit layer of the ceramic substrate forms an L-shaped top circuit layer through an etching process, and the thickness of one side, processed through the etching process, of the top circuit layer is small; the power transistor wafer is welded on the top surface of one side with smaller thickness of the L-shaped top circuit layer of the ceramic substrate through the drain electrode bonding pad; the insulating rubber material is filled around the power transistor wafer horizontally. The ceramic substrate is used as a drain electrode conductive pole piece of the power transistor wafer, a packaged drain electrode bonding pad, a cooling fin and a substrate at the same time; through the insulation performance and the high thermal conductivity of the ceramic substrate layer, a cooling fin can be directly arranged on the bottom circuit layer of the ceramic substrate, and the heat dissipation performance of the power device is improved.

The invention discloses a wafer-level Micro LED (Light Emitting Diode) chip packaging structure and a packaging method thereof. The wafer-level Micro LED chip packaging structure comprises a bearing substrate, a wafer-level Micro LED chip, a wafer-level Micro LED chip and a packaging substrate, the at least one LED chip and the at least one first electrode disc are arranged on the bearing substrate, each LED chip comprises a first chip electrode and a second chip electrode which are located on the two sides of the LED chip, the first chip electrode is adjacent to the bearing substrate and electrically connected with the first electrode disc, the second chip electrode deviates from the bearing substrate, and a second electrode disc is arranged on the second chip electrode; the second electrode disc is electrically connected with the second chip electrode; and the bonding pad surfaces of the first electrode plate and the second electrode plate, which deviate from the bearing substrate, are approximately positioned on the same horizontal plane relative to the bearing substrate. By the adoption of the packaging structure and the packaging method, the packaging process is simple, reliability is high, wafer-level efficient packaging and system integration of the Micro LED chip can be conveniently achieved, the packaged Micro LED chip integrated device is easily connected with an application substrate in an overall surface-mounting mode, and therefore production efficiency is greatly improved.

This invention provides an all-solid-state ionized pressure sensor based on a gradient micro-pyramid array and a modulus-matched cross-linking interface, along with its fabrication method and applications, belonging to the field of sensor technology. The all-solid-state ionized pressure sensor of this invention includes a lower encapsulation layer, a lower electrode layer, a gradient micro-pyramid array dielectric layer, an upper electrode layer, and an upper encapsulation layer stacked sequentially. By constructing a modulus-matched cross-linking interface between the dielectric layer and the electrode layer, this invention effectively enhances the interfacial bonding strength between the multilayer structures, suppresses signal drift caused by interfacial slippage and delamination under cyclic loading and complex deformation conditions, and improves the signal stability and repeatability of the sensor during long-term operation and dynamic loading. Combined with a highly gradient-distributed micro-pyramid array structure synergistically constructed from fumed silica and an organic electrolyte, the dielectric layer achieves stepwise response and controllable deformation over a wide pressure range, broadening the linear response range of the ionized sensor.

The invention relates to a packaging body of a semiconductor tube core and a manufacturing method of the packaging body of the semiconductor tube core, and in the manufacturing method of the packaging body of the semiconductor tube core, in the process of preparing an initial packaging substrate, a second insulating layer and a second metal layer are respectively arranged on two first conductive circuit layers in a stacked manner; the second metal layer on the lower layer is patterned to form a first shielding layer, the first shielding layer is located below the conductive bonding pad, and then a second shielding layer is formed at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected, and the second conductive block and the first shielding layer are electrically connected. The first shielding layer and the second shielding layer effectively surround the first semiconductor tube core, so that the first semiconductor tube core can be effectively prevented from being interfered by electromagnetic interference.

The application provides a collimating device and a preparation method. The collimating device comprises a first substrate, a second substrate and a sealing material. The first substrate has a first sealing surface. The second substrate has a second sealing surface. The sealing material is arranged on the first sealing surface and / or the second sealing surface. The sealing material is solidified to form a borate glass sealing layer so that the first sealing surface and the second sealing surface are sealed by the sealing material. The sealing material comprises silica, alkali metal oxide, alkaline earth metal oxide, carbonate and water. The sealing material is in a fluid state before solidification.

The utility model relates to the technical field of SSR optocouplers, in particular to a support structure of a vertical SSR optocoupler. Through the symmetrical design of the PT support and the IR support and the opposite distribution of the PT base island and the IR base island, the direct light path alignment of the light emitting diode and the bidirectional photosensitive silicon controlled rectifier is realized, the light transmission efficiency is obviously improved, the L-shaped output pin extends to the end part of the adjacent pin, and the PT base island is arranged, so that the bidirectional silicon controlled rectifier and the photosensitive silicon controlled rectifier are respectively arranged on different base islands, and the light transmission efficiency is improved. The risk that insulating glue overflows to the photosensitive silicon controlled rectifier chip is avoided, the short circuit probability is reduced, meanwhile, the discrete base island layout optimizes a conductive path, the number of conductive wires is reduced to the minimum, the gold wire material cost and quality hidden dangers such as wire collapse and wire breakage in the wire welding process are reduced, and the production yield and the product reliability are improved; the technical problems that after an existing SSR optocoupler support structure is packaged into an SSR optocoupler, the light transmission efficiency is low, glue is prone to overflowing to form a short circuit, and the number of electric leads is large are solved.

The utility model relates to the technical field of power electronic silicon stack devices, in particular to a silicon carbide patch type ceramic diode. Comprising a ceramic shell, a silicon carbide chip, a lead-in electrode, a lead-out electrode, a copper-clad substrate and a bonding copper sheet, the silicon carbide chips are fixedly connected to the copper-clad substrates, the multiple copper-clad substrates are distributed in a matrix mode, the ceramic shell is of a rectangular box structure with an opening, grooves corresponding to the copper-clad substrates are formed in the inner bottom face of the ceramic shell, and the copper-clad substrates are embedded into the grooves. The leading-in electrode and the leading-out electrode are fixedly connected to the two sides of the copper-clad substrate matrix and connected with the copper-clad substrate and the silicon carbide chip through the bonding copper sheets. And the copper-clad substrates are connected through bonding copper sheets. The heat conductivity can be improved, the packaging process is simplified, and the overall performance is improved.

The present application relates to the technical field of insulation film, especially to the field of IPC G03F, more particularly to a preparation method of a photosensitive integrated circuit stacked insulation film. The present application is based on the actual market demand, and scientifically designs the formula of the stacked insulation film material by combining basic research with industrial development, so as to realize the manufacturing of the fine line laminated adhesive film with low thermal expansion coefficient, high frequency low dielectric, low loss, high bonding force. The material has good performance in insulation, mechanics, heat conduction and the like, and does not depend on the expensive precision drilling equipment imported, and these performances enable it to replace ABF in the electronic field such as microchip integrated insulation technology, and have wide application prospect.

The invention discloses a circular capacitive MEMS microphone packaging structure and process, and belongs to the technical field of semiconductor packaging. The structure comprises a PCB substrate adopting a circular design, and the substrate is provided with a through hole so as to form a front cavity with a self-contained cavity of an MEMS capacitive chip; the ASIC integrated chip and the MEMS capacitive chip are mounted on the substrate and are electrically connected with each other; the circular shell covers the periphery of the substrate, and a circular expansion back cavity surrounding the double chips is formed in the circular shell. The process comprises the steps of substrate dispensing and chip mounting, baking and curing, gold wire bridging, COB glue dispensing and coating, tin drawing, shell reflow soldering and curing and the like. According to the invention, through the cooperation of the circular substrate and the housing, the space of the back cavity is increased, and the SNR signal-to-noise ratio performance is effectively optimized; meanwhile, according to the packaging structure, the harsh requirement for the height of chip glue is lowered, the technological process is simplified, the operation cost is lowered, and product miniaturization and performance optimization are facilitated.

An aluminum substrate power device package comprises a power transistor wafer, an aluminum drain electrode bonding pad is arranged on the bottom face of the power transistor wafer, and a source electrode bonding pad and a switch control electrode bonding pad are arranged on the top face of the power transistor wafer. The power transistor further comprises an L-shaped aluminum substrate, the thickness of one side of the L-shaped aluminum substrate is small, and the power transistor wafer is welded to the top face of the side, with the small thickness, of the L-shaped aluminum substrate through an aluminum drain electrode bonding pad. The insulating rubber material is filled around the power transistor wafer horizontally. The L-shaped aluminum substrate is simultaneously used as a drain electrode conductive pole piece of the power transistor wafer, a packaged drain electrode bonding pad, a packaged cooling fin and a packaged substrate; through the aluminum-aluminum welding process, the wafer is welded on the L-shaped aluminum substrate, so that the processing links are reduced, the cost is saved, the performance of a power device is improved, and high-power transistor packaging with high cost performance is realized.

This application discloses a perovskite solar cell and its fabrication method. The perovskite solar cell of this application comprises a substrate, a transparent electrode, a functional layer, a back electrode, and an encapsulation layer stacked sequentially. The encapsulation layer is formed by directly coating an encapsulation material slurry onto the back electrode and then curing it. The encapsulation material slurry includes a main encapsulation material and thermally conductive nanoparticles dispersed therein. This perovskite solar cell offers the advantages of coating encapsulation. By adding thermally conductive nanoparticles to the encapsulation layer, an efficient heat dissipation network is constructed, effectively dissipating internal heat, inhibiting thermal degradation of the perovskite material, and significantly improving its lifespan. The barrier effect of the thermally conductive nanoparticle network synergistically enhances water and oxygen barrier performance. This perovskite solar cell has advantages such as good encapsulation effect, strong thermal conductivity, long lifespan, simplified encapsulation process, and low cost, making it suitable for the efficient and continuous mass production of large-area flexible perovskite solar cells.