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Method and system for single time slot numerically controlling attenuation

A digitally controlled attenuation and single-slot technology, applied in transmission systems, transmission control/equalization, electrical components, etc., can solve the problem of inability to reduce cell interference, failure to reach signal coverage, and increased power consumption of user terminal equipment, etc. problems, to achieve the effect of protecting normal operation, improving system stability, compatibility and anti-interference ability, and protecting against interference

Active Publication Date: 2008-07-16
SHENZHEN GRENTECH RF COMM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that since the power of each subframe in the TD-SCDMA system is inconsistent, attenuating a fixed value for all time slots may cause some time slots with higher power to still have relatively high power after attenuation. It cannot play the role of reducing the interference in the cell and between cells; while attenuating some time slots with low power, the power of the time slot may become very small after the attenuation, and the expected signal coverage cannot be achieved. It may also lead to increased power consumption of user terminal equipment

Method used

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  • Method and system for single time slot numerically controlling attenuation
  • Method and system for single time slot numerically controlling attenuation
  • Method and system for single time slot numerically controlling attenuation

Examples

Experimental program
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Effect test

Embodiment 1

[0088] Step S301, setting a time delay, and obtaining synchronization information.

[0089] Step S302, detecting the output powers of TS0, TS1, TS2, TS3, TS4, TS5 and TS6.

[0090] The TD-SCDMA signal is provided by the RF module, and the sampling power intensity is obtained through ADC detection; because there is always a certain distance between the base station and the repeater link, and there is also a certain distance between the end user's mobile phone and the base station, we can monitor and set , which is transmitted to the FPGA of the synchronization module, and the FPGA compensates the delay control amount to ensure the accuracy of the link power detection value;

[0091] The synchronization control module FPGA finds out the uplink and downlink time slots, the position of the switching point and the position of the training sequence code of each time slot according to the power intensity provided by the ADC sampling and the time feature of TD-SCDMA, according to the ...

Embodiment 2

[0099] Step S401 , setting a time delay, and obtaining synchronization information.

[0100] Step S402, detecting the input power and output power of TS0, TS1, TS2, TS3, TS4, TS5 and TS6.

[0101] The TD-SCDMA signal is provided by the RF module, and the sampling power intensity is obtained through ADC detection; because there is always a certain distance between the base station and the repeater link, and there is also a certain distance between the end user's mobile phone and the base station, we can monitor and set , which is transmitted to the FPGA of the synchronization module, and the FPGA compensates the delay control amount to ensure the accuracy of the link power detection value.

[0102] The synchronization control module FPGA finds out the uplink and downlink time slots, the position of the switching point and the position of the training sequence code of each time slot according to the power intensity provided by the ADC sampling and the time characteristics of TD-...

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Abstract

The invention discloses a single-time slot digital control attenuating method and a system thereof, wherein the method comprises the following steps: the power value of each time slot is detected; according to the detected power value and system requirements, the attenuation value of the time slot is set; the attenuation value is converted into control signal and is transmitted to a control circuit, thereby realizing attenuation of the time slot. The system comprises a sampling module, an FPGA module, an MCU and an attenuation control circuit, wherein the sampling module is used to acquire sampling power value through ADC detection; the FPGA module is used to compensate time delay control quantity and to find out uplink time slot, downlink time slot, the address of a switching point and the address of the training sequence code of each time slot according to a time characteristic window; moreover, according to the power value and the time characteristics of TD-SCDMA signal, the FPGA module can obtain the power value of each time slot. By means of the characteristics of a TD-SCDMA system, the invention realizes digital control attenuation of each time slot of each subframe of a wireless frame, thereby effectively controlling the output power of each time slot.

Description

【Technical field】 [0001] The invention relates to a time-division system in the communication field, in particular to a method and system for digitally controlled attenuation of a single time slot. 【Background technique】 [0002] The biggest difference between the TD-SCDM system and other 3G systems lies in the different physical layer technologies. In the TD system, the uplink and downlink channels use the same frequency, and each wireless frame is 10ms long. TD-SCDMA divides each wireless frame into two 5ms subframes, and the frame structures of the two subframes are exactly the same. [0003] As shown in Figure 1, each subframe consists of 7 regular time slots (TS0-TS6) with a length of 675us and 3 special time slots (downlink pilot time slots DwPTs, guard interval GP and uplink pilot time slots UpPTs) . Conventional time slots are used to transmit user data or control information, TS0 is always used as a downlink time slot to send system broadcast information, and TS1...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B7/005H04B1/707H04W52/04
Inventor 戴小华李保华
Owner SHENZHEN GRENTECH RF COMM LTD
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