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Method for interconnecting multilayer phase transition memory array and lower layer peripheral circuit

A technology of phase-change storage and peripheral circuits, applied in circuits, information storage, static memory, etc., can solve problems that are not conducive to low voltage and low power consumption of chips

Inactive Publication Date: 2008-07-30
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Strict requirements on area will inevitably lead circuit designers to give up performance in terms of speed and power consumption in exchange for area, which is not conducive to the realization of low-voltage, low-power consumption, high-speed and high-density chip design

Method used

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  • Method for interconnecting multilayer phase transition memory array and lower layer peripheral circuit
  • Method for interconnecting multilayer phase transition memory array and lower layer peripheral circuit
  • Method for interconnecting multilayer phase transition memory array and lower layer peripheral circuit

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Experimental program
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Embodiment 1

[0022] As shown in Figure 2, the storage units of each layer are aligned up and down. Except that the phase-change memory array of the first layer can be directly connected with the peripheral circuit of the bottom layer, all word (or bit) lines of the layers above the first layer are introduced into the peripheral circuit of the bottom layer through the through holes arranged at the edge of the memory array. Due to the relatively small area occupied by the through holes, the area of ​​the limited number of through holes is almost negligible under a large-capacity memory chip. The top view of the overall layout is shown in Figure 3.

[0023] As a feasible optimization method, if the area requirement is not very strict, the series resistance of the vias can be reduced by increasing the number of vias. As shown in Figure 4, a plurality of through holes are added at the edge of the memory array.

[0024] In theory, this method can connect storage arrays of any level. However, ...

Embodiment 2

[0026] Leading out the word (or bit) line at the edge of the memory array will concentrate the bottom peripheral circuits on the edge of the memory array, which may cause difficulties in the design of the bottom circuit.

[0027] Another method proposed in this embodiment can prevent the interconnection lines from being concentrated on the edge of the storage array. The memory cells of the upper layer and the memory cells of the lower layer are staggered by a certain distance to allow a certain distance of through holes. As shown in FIG. 5 , the squares with thin solid lines represent the first layer memory cells, the squares with dashed lines represent the second layer memory cells, the small black holes in the squares represent through holes, and the rectangles with thick solid lines represent word line metals. Assume that the minimum side length of the memory cell is b, the minimum distance between the memory cells is m; the size of the through hole is a, and the minimum di...

Embodiment 3

[0031] There is a limit to the number of layers in the staggered arrangement of memory cells. In order to break through this limitation and at the same time facilitate the design of the underlying circuit, this embodiment proposes a method for sharing word lines by memory cells of different levels.

[0032] As shown in Figure 7, the memory cells of all levels are aligned, and the gap between the memory cells is used to drill through holes so that the word lines between the upper and lower layers are connected together. Since the bit lines of each memory cell between the upper and lower layers are not connected to each other, from the perspective of the peripheral circuit, it is equivalent to adding more memory cells on the word line. Within the allowable range of design rules, the area of ​​the through hole will not affect the overall area of ​​the memory array.

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Abstract

The invention relates to a method for interconnecting a multilayer phase change memory array with an underlayer peripheral circuit, which can achieve the interconnection between an over-layer phase change memory array with the underlayer peripheral circuit by a certain interconnecting manner. The invention is characterized in that the invention provides four interconnecting manners such as edge interconnect, staggered interconnect, interconnect sharing word line and interconnect integrated the above three manners. Each interconnecting manner is analyzed to determine the advantages and disadvantages and the general application range, thus achieving the multilayer phase change memory chip design of high-density and large-capacity.

Description

technical field [0001] The invention relates to a method for interconnecting a multi-level phase-change storage array and a lower peripheral circuit. Specifically, it is a solution to the problem of interconnecting the 1R1D phase-change memory array with the three-dimensional multi-level structure and the lower peripheral circuit. Background technique [0002] Chalcogenide-Random Access Memory (C-RAM) is based on S.R. Ovshinsky in the late 1960s (Phys. Rev. Lett. 21, 1450-1453, 1968) and early 1970s (Appl. Phys. Lett.18, 254-257, 1971) was developed on the basis of the idea that the chalcogenide thin film can be applied to phase-change storage media. In 2001, Intel Corporation reported 4MB of C-RAM for the first time. By the end of 2006, South Korea's Samsung Corporation had reported 512MB of C-RAM. At present, the mainstream non-volatile memory is mainly flash memory. However, according to Moore's law, when the existing memory cell design is below 45nm, it is difficult t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/24H01L23/522G11C11/56G11C16/02
Inventor 宋志棠丁晟刘波宝民封松林刘卫丽
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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