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Double CPU protection information shared system and information processing method based on double port RAM

A technology for protecting information and sharing systems, applied in the field of hardware systems, can solve problems such as large space occupied by computing programs, less program space, and device inheritance limitations, so as to reduce research and development costs and production costs, smooth the development process, and shorten the development cycle Effect

Active Publication Date: 2008-08-13
NANJING GUODIAN NANZI POWER GRID AUTOMATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The main frequency of the control system of the original protection device is low, and the program space is small, which is increasingly unable to meet the requirements of the current protection device.
At present, the control system of the protective device mostly adopts a single CPU system with high frequency and complex operation. All control calculation functions are completed by one CPU. For different or higher hardware requirements, it is necessary to replace all the control systems when upgrading. system, which limits the inheritance of the device, is not easy to upgrade, increases the cost and reduces the efficiency
At the same time, in terms of information processing, since a single CPU system is used, the protection information used is also calculated by itself, and the calculation program to confirm its correctness takes up a large space, and on-site electromagnetic interference is likely to cause distortion of protection information, reliability and real-time sex is not enough

Method used

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  • Double CPU protection information shared system and information processing method based on double port RAM
  • Double CPU protection information shared system and information processing method based on double port RAM
  • Double CPU protection information shared system and information processing method based on double port RAM

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Experimental program
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Effect test

Embodiment 1

[0022] When the dual-CPU protection information sharing system based on dual-port RAM in this embodiment is used in situations where protection information requires high real-time performance and low reliability requirements, the specific working process is shown in FIG. 3 . The information providing system (such as the system CPUA) stores the protection information group Z in the dual-port RAM chip U in real time during the 600Hz or 1200Hz periodic interrupt; the information using system (such as the system CPUB) uses any protection information in the protection information group Z When X, the information will be read from the dual-port RAM chip U, and the algorithm with strong anti-interference ability will be used for protection calculation, which satisfies the information sharing between the two CPUs and ensures the real-time performance of the information. .

Embodiment 2

[0024] This embodiment is a technical solution formed by further analysis and changes based on embodiment 1, and it is used in situations where the protection information group requires high real-time performance and high reliability. The specific working process is shown in FIG. 4 . The system CPUA stores the protection information group Z in the dual-port RAM chip U in real time during the 600Hz or 1200Hz periodic interrupt, and redundantly stores the protection information group three times in the adjacent area of ​​the dual-port RAM chip; the system CPUB uses the protection When any protection information X in the information group Z is used, the result obtained after "ANDing" the protection information X and its corresponding three redundant information is used for protection calculation, so as to ensure that the information will not cause system error when the protection information X is wrong. move.

[0025] In this way, since the system CPUA is constantly updating the ...

Embodiment 3

[0027]This embodiment is a technical solution further modified on the basis of the above embodiments, and is used in situations where the real-time performance of protection information is not high and reliability is important. The specific working process is shown in FIG. 5 . When the system starts or the protection information is modified, the system CPUA stores the protection information group Z in the dual-port RAM chip U, and stores its inverse code and XOR code in the adjacent area. When the system CPUB uses any protection information X in the protection information group Z, it checks the protection information X by inverse code and XOR code. If the check is correct, it will continue to run. If the check is incorrect, the system CPUB will Automatically stop using the protection information X, and set the reliability flag F to inform the system CPUA. The system CPUA uses two methods to check the reliability of the protection information group Z during operation: 1. Scan t...

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Abstract

The present invention provides a double CPU conservation information sharing system and information processing method based on double-port RAM, the characteristics of the sharing system is that the system includes two CPU system of system CPUA and CPUB, a double-port RAM chip, two CPU system, connecting to the ends of double-port RAM chip respectively, relay protection operation distributed in two CPU system of CPUA and CPUB, each CPU system completing different part of the operation, double-port RAM chip sharing alternating protection information of two CPU system. The invention checks the protection information, meeting requirement of the high operational capability and speed, ensuring information credibility and real-time. The system combines the high performance, credibility and easy updating of the protection device accompanied by design principle of high performance and lower hardware requirement, reducing cost of equipment, research.

Description

technical field [0001] The invention relates to a hardware system and an information processing method for realizing safe real-time sharing of protection information between two CPU systems through a dual-port RAM chip in a protection device. Background technique [0002] As the integration of relay protection devices in the power system becomes higher and higher, a single protection device undertakes more and more protection functions, and the calculation and control tasks undertaken by the control system in the device become heavier and heavier, which requires the device to provide computing speed Fast, powerful CPU system to meet this requirement. [0003] The main frequency of the control system of the original protection device is low, and the program space is small, which is increasingly unable to meet the requirements of the current protection device. At present, the control system of the protective device mostly adopts a single CPU system with high frequency and com...

Claims

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Application Information

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IPC IPC(8): G06F15/76G06F13/00
Inventor 包明磊丁俊健
Owner NANJING GUODIAN NANZI POWER GRID AUTOMATION
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