Complete package data transmission method and transmission system

Abstract

The invention discloses a transmission method and a transmission system for the integral packet data, including the steps that the data signal and the state signal are transmitted in parallel by the sender; the data signal includes the data signal of the data packet; the state signal includes the state signal which indicates the transmission state of the data packet; wherein, the data signal of the data packet is transmitted at least in three times; the receiver receives the state signal and the data signal and stores the data signal according to the state signal; wherein, the receiving mode is that the data signal of the same data packet received in the continuous clock cycle is stored in the continuous storage space. In the transmission method and the transmission system for the integral packet data, the data signal and the state signal are separated for parallel transmission; thereby, the state signal can not occupy the transmission bandwidth of the data signal; otherwise, the packet reintegration is avoided in the receiver; the data signal received in the continuous clock cycle is stored in the continuous storage space in the receiver; the data transmission process is simplified and the transmission speed is improved.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method and system for transmitting whole-packet data. Background technique [0002] With the progress of chip manufacturing technology and other aspects of technology, the transmission speed of various chip interfaces is gradually increasing. Taking communication chips as an example, the interface speed of communication chips has increased from 100Mb / s and 155Mb / s a few years ago to 622Mb / s, later increased from 622Mb / s to 2.5Gb / s, and now increased from 2.5Gb / s to 10Gb / s. The continuous improvement of chip interface traffic has also prompted the emergence of new high-speed transmission methods and high-speed interface systems. [0003] When the above-mentioned high-speed interface transmits a data packet, the data packet usually contains more data signals, so the interface cannot be transmitted at one time, that is, one clock cycle, so the data packet is usually divid...

AI Technical Summary

Problems solved by technology

Because the status signal is inserted into the data signal in this method, the bandwidth of the data bus is occupied, so that the utilization rate of the bandwidth of the data signal is less than 80%.

However, the data transmission at the receiving terminal of the interface is in the form of a whole packet, that is, a data packet is stored in the 64-bit data sent by the continuous clock, so that the 64-bit data received by the SPI interface in continuous clock cycles is a data packet , so there is no need for packet reassembly. However, the fixed packet reassembly mode of the SPI interface makes the interface redundant, more complex, and the speed cannot be better utilized.

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