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Adhesive film for stacking semiconductor chip

A technology of adhesive film and semiconductor, applied in the direction of film/sheet adhesive, semiconductor device, semiconductor/solid device manufacturing, etc., can solve the problem that it is impossible to stack 3 or more layers of chips Problems such as the same integration and inability to achieve stacking

Active Publication Date: 2008-09-17
TORAY ADVANCED MATERIALS KOREA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the stacking area in the upper chip layer and the lower chip layer is made different, for example, the area of ​​the wires in the upper chip layer used to stack the chips is smaller than the area of ​​the lower chip layer, then the aforementioned problem is solved, however, the stacked chips are constructed as a pyramid , making it impossible to achieve the same integration, and such a stacking scheme can only be used for up to two layers
Therefore, a stack of at least three layers with the same area cannot be basically realized
[0008] Therefore, it is impossible to stack 3 or more layers of chips with the existing technology using both spacers and adhesive films

Method used

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  • Adhesive film for stacking semiconductor chip
  • Adhesive film for stacking semiconductor chip
  • Adhesive film for stacking semiconductor chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach

[0063] Sample 1: Making the first and third adhesive layers of epoxy

[0064] First, 100 parts by weight of cresol novolak epoxy resin (YDCN8P, commercially available from Toto Kasei Co.), 50 parts by weight of phenol novolac resin (KPH2000, commercially available from Kolon Chemical Co.), 0.02 parts by weight of 1 - a mixture of cyanoethyl-2-phenylimidazole (CURESOL 2PZ-CN, commercially available from Shikoku Kasei Co.) for 3 hours. Subsequently, 50 parts by weight of a phenoxy resin (YP50, commercially available from Toto Kasei Co.) was added to the stirred mixture, and then the mixture was further stirred for 6 hours. The resulting stirred mixture was spread on a substrate of release-treated polyethylene terephthalate film to a thickness of 38 μm. The coated film was then dried at 90° C. for 3 minutes to produce a B-staged 40 μm thick first adhesive layer and a B-staged 10 μm thick third adhesive layer.

[0065] Sample 2: Making a Second Adhesive Layer of Phenoxy Resi...

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Abstract

The invention concerns an adhesive film for stacking chips which enables chips to be stacked in layers without using a separate spacer usually provided to keep a given distance between wires of an upper chip and a lower chip to have the same area. The adhesive film of the invention has an intermediate adhesive layer of thermoplastic phenoxy resin on both side of which a thermosetting adhesive layer of epoxy resin is placed, respectively, to make a three-layer structure, the thermoplastic phenoxy resin comprising UV curable small molecule compounds. The adhesive film of the invention is a multi-layered adhesive film produced by a method of comprising the steps of achieving compatibility on an interface between the thermosetting epoxy resin and thermoplastic phenoxy resin and then directly forming a phenoxy film of a high elastic modulus through UV curing in an adhesive film. With such a configuration, the adhesive film for stacking semiconductor chips according to the invention enables the semiconductor silicone chips to be stacked in 3 or more layers without using a separate spacer between chips in order to keep a wire distance between upper and lower chips in stacking the chips. With the configuration, it is advantageous that reliability of semiconductors is not lowered because adhesiveness is kept despite of a repeated process of stacking chips subject to high temperature.

Description

technical field [0001] The present invention relates to an adhesive film for stacking semiconductor chips, and more particularly, to an adhesive film for stacking semiconductor chips that allows at least 3 layers of chips having the same area to be stacked, Without using any separate spacer, which is sandwiched between the upper and lower chips to maintain the line-to-line distance between the upper and lower chips in stacked semiconductor silicon chips, and the adhesive film undergoes repeated stacking at high temperatures Adhesion can be preserved during the process to thereby ensure the reliability of the semiconductor. Background technique [0002] In general, in order to increase the integration of semiconductors, a method of stacking several layers of silicon chips by effectively using spacers in semiconductor packages is widely used. In order to effectively use this stacking method, a wafer backside lamination structure (WBL) is used in which an adhesive film is firs...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C09J7/02H01L25/00C09J7/10
CPCC09J2463/00H01L2224/83101H01L25/0657C09J7/00H01L24/83H01L2225/06575H01L2224/32145H01L2225/0651C09J2461/00H01L2924/01078H01L2924/10253H01L2224/83856H01L2924/01012H01L2224/48091H01L2924/01087H01L2224/73265C09J2201/36H01L2924/01077H01L2224/26135H01L2224/29083H01L2924/351C09J7/10Y10T428/28Y10T428/2848Y10T428/2852Y10T428/287Y10T428/24975Y10T428/31511C09J2301/208H01L2924/00014H01L2924/3512H01L2924/00H01L23/12H01L21/50
Inventor 沈昌勋文基祯全海尚李準浩朴允敏
Owner TORAY ADVANCED MATERIALS KOREA
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