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Semiconductor memory device using ferroelectric device and method for refresh thereof

A memory and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, static memory, etc., can solve the problems of increasing power consumption and reducing performance

Inactive Publication Date: 2012-07-11
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, frequent update operations increase power consumption and degrade performance

Method used

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  • Semiconductor memory device using ferroelectric device and method for refresh thereof
  • Semiconductor memory device using ferroelectric device and method for refresh thereof
  • Semiconductor memory device using ferroelectric device and method for refresh thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0067] figure 1 is a cross-sectional view showing a semiconductor memory device.

[0068] A one-transistor (1-T) field effect transistor (FET) type ferroelectric memory cell includes a p-type channel region, an N-type drain region 2 and an N-type source region 3 formed in a p-type region substrate 1 . A ferroelectric layer 4 is formed over the channel region, and a word line 5 is formed over the ferroelectric layer 4 .

[0069] For process stability, a buffer insulating layer 6 may be formed between the channel region and the ferroelectric layer 4 . That is, buffer insulating layer 6 is formed to eliminate process and material differences between the channel region and ferroelectric layer 4 .

[0070] The semiconductor memory device reads and writes data in response to the channel resistance of the memory cells differentiated according to the polarization state of the ferroelectric layer 4 .

[0071] When the polarity of the ferroelectric layer 4 induces positive charges in...

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Abstract

A semiconductor memory device with a ferroelectric device comprises a channel region, a drain region and a source region formed in a substrate, a ferroelectric layer formed over the channel region, and a word line formed over the ferroelectric layer. A different channel resistance is induced to the channel region depending on a polarity state of the ferroelectric layer, a data read operation is performed by a cell sensing current value differentiated depending on the polarity state of the ferroelectric layer while a read voltage is applied to the word line and a sensing bias voltage is applied to one of the drain region and the source region, and a data write operation is performed by a polarity of the ferroelectric layer changed depending on a voltage applied to the word line, the drain region and the source region.

Description

technical field [0001] Embodiments consistent with the present invention generally relate to semiconductor memory devices having ferroelectric devices and methods of updating the same, and more specifically, to integrating a transistor-field effect transistor (1T-FET) type ferroelectric The electrical memory cell is a technology used in dynamic random access memory (DRAM). Background technique [0002] Generally, in order to store data in DRAM like a volatile memory, power should be supplied continuously. When the power supply is cut off momentarily, the data of RAM may be destroyed because the memory cells of DRAM are designed based on small charged electrons used to store the charge source. If these charged electrons are not continuously recharged, the power of the previous charge can be destroyed. [0003] The refresh operation refers to the recharging process of the memory chip unit. In each refresh cycle, a row of memory cells can be charged. Although the refresh op...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/22H01L27/108H01L23/522H10B12/00
CPCG11C8/08G11C8/10G11C11/22G11C11/5657H10B53/00H10B51/00
Inventor 姜熙福洪锡敬
Owner SK HYNIX INC