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Jitter-tolerance-enhanced cdr using a gdco-based phase detector

A technology of digitally controlled oscillation and controlled oscillator, applied in multiple input and output pulse circuits, digital transmission systems, automatic power control, etc., and can solve problems such as power consumption and increase in chip layout area.

Inactive Publication Date: 2008-10-01
MEDIATEK INC +1
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  • Claims
  • Application Information

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Problems solved by technology

Although this method is effective, power consumption and chip layout area will also increase

Method used

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  • Jitter-tolerance-enhanced cdr using a gdco-based phase detector
  • Jitter-tolerance-enhanced cdr using a gdco-based phase detector
  • Jitter-tolerance-enhanced cdr using a gdco-based phase detector

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Embodiment Construction

[0044] Although there are many theories for predicting jitter transfer and jitter tolerance in bang-bang data and clock recovery circuits, non-linearity and input-dependent jitter transfer make design more difficult, especially in applications where some loop characteristics must be well defined. To pass jitter transfer and jitter tolerance specifications, linear data and clock recovery circuit architectures are most commonly used. Assume that the phase of the input data and a known phase of the data and the output of the clock recovery circuit are φ D (s) and φ OUT (s). Therefore, in the jitter transfer H(s), and the jitter tolerance J TOL (s) can be expressed in the representation of the S field as follows:

[0045]

[0046] Wherein UIpp in formula (5.1b) indicates that the peak-to-peak jitter amplitude is normalized within a unit interval. However, the jitter tolerance in Equation (5.1b) is very optimistic, assuming ideal conditions for the data and clock recovery s...

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Abstract

The invention provides a data and clock pulse reflex circuit and a grid type digital control oscillator. The data and clock pulse reflex circuit comprises a first data and clock pulse reflex circuit and a second data and clock pulse reflex circuit. The first data and clock pulse reflex circuit receives a data signal and a reference signal and performs demultiplex of the data signal to generate a first signal and a second signal, wherein the data signal has a first data transmission rate 2X bps, and the first signal and the second signal have a second data transmission rate X bps. The second data and clock pulse reflex circuit receives and reduces the oscillation in the first signal and the second signal for outputting a first reflex signal and a second reflex signal, wherein the bandwidth of the first data and clock pulse reflex circuit is wider than that of the second data and clock pulse reflex circuit.

Description

technical field [0001] The present invention relates to a data and clock recovery circuit, in particular to a data and clock recovery circuit using a phase detector based on a grid-type digitally controlled oscillator and having high jitter tolerance. Background technique [0002] Jitter tolerance is related to the maximum amplitude of sinusoidal jitter, which can be regarded as a function of frequency. The known phase-tracking (phase-tracking) data and clock recovery circuit (clock an data recovery circuit, CDR) has a jitter tolerance that is inversely proportional to the jitter frequency (jitter frequency), so it is necessary to increase the bandwidth of the CDR Change the loop parameters (loop parameters) to accommodate more high-frequency jitter. However this may increase jitter transfer and may not be suitable for some applications such as data repeaters. The trade-off between jitter transfer and jitter tolerance limits the design margin and any non-idealities, such a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/02H04L7/033H03L7/06H03L7/18H03L7/099H03K5/26
CPCH04L7/033H03L7/07H03L7/0805H03L7/0807H03L7/0995H04J3/047H04L7/027
Inventor 刘深渊梁哲夫胡思全
Owner MEDIATEK INC
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