Phase-change memorizer driver circuit
A phase-change memory and driving circuit technology, applied in the design of phase-change memory drive circuits and the field of phase-change memory drive circuits, can solve the problems of not considering the difference of GST unit resistance, and achieve optimized circuit design, ensure consistency, and improve heating. The effect of efficiency
Inactive Publication Date: 2008-10-15
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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Problems solved by technology
However, in this method, since the MOS gate transistors in each unit have different lining bias effects at this time, they have different on-resistance under the same gate voltage, and the difference in the resistance of the GST unit itself is not considered, so the drive current consistency problem still not well resolved
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[0037] The following is based on Figure 5-Figure 14 The preferred embodiments of the present invention are given and described in detail so that those skilled in the art can better understand the structural features and functional features of the present invention, rather than to limit the scope of the present invention.
[0038] according to Figure 5 The schematic diagram of the internal circuit of the phase change memory chip mainly includes a phase change memory cell array, an address decoder (row line selection circuit and bit line selection circuit), a read and write drive circuit, a drive control circuit and a sense amplifier circuit. The phase change memory cell array includes a number of word lines, a number of bit lines and a number of phase change memory cells at the intersection of the word lines and the bit lines, and each memory cell includes a word line, a gate transistor and a phase change memory cell. Variable resistance, and each phase change resistance can...
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The invention relates to a drive circuit of a phase-change storage, which is characterized in that a double-level current mirror structure is adopted, the first level is a current mirror circuit formed by NMOS tubes, the second level is the current mirror circuit formed by PMOS tubes, the first-level current mirror circuit and the second-level current mirror circuit are connected with each other, and the output signals of the second level are finally coupled with a bit line. A control switch is added between the first-level current mirror circuit and the second-level current mirror circuit so as to control a pulse time sequence which reads, writes and erases an operating current. The second-level current mirror circuit of the current mirror structure adopts a cascode or an improved cascode current structure and can inhibit the influence of the channel length modulating effect of the current mirrors in the drive circuit, thus leading the image current error of the drive circuit of the phase-change storage to be decreased or eliminated, leading the influence of a backstage load on a forestage circuit to be weak, and achieving current uniformity. The drive circuit of the phase-change storage, which is provided by the invention, is a current pulse circuit which drives the phase-change storage unit to generate reversible phase change and realize information storage.
Description
technical field [0001] The present invention relates to a phase-change memory drive circuit, more specifically, it is a phase-change memory drive circuit design for which the generated current pulses are applied to different memory cells to achieve good consistency and the falling edge is controllable , the circuit can ensure the smooth progress of the phase change process of the phase change unit, and belongs to the technical field of large scale integrated circuits. Background technique [0002] Phase change memory is a new type of memory. With the development of technology and technology, the size of materials in devices can be reduced to the nanometer level, and the voltage and power consumption required for the phase change of materials are greatly reduced. In the fierce competition for the development of next-generation high-performance non-volatile memory technology, phase change memory has shown great competitiveness in terms of read and write speed, read and write t...
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IPC IPC(8): G11C11/56
Inventor 宋志棠沈菊刘波封松林
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI