Capacitor layer manufacturing method in DRAM

Abstract

The invention provides a method for manufacturing capacitance layers in DRAM. The method comprises six main steps: 1, photoresistors are developed on a DRAM wafer with a protective layer in an arrangement mode like black squares or white squares on a chessboard; 2, the protective layer is etched, and a protective-layer part under the photoresistors is reserved; 3, an insulating layer is deposited; the tops of protective blocks and insulating objects among the protective blocks are removed; and insulating objects on the sides of the protective blocks are reserved; 4, the protective blocks are dug out, and the insulating objects on the sides of the protective blocks are reserved, so as to form an insulating-object mullion; 5, a bottom electrode layer is deposited, and a bottom electrode layer part on the top of the insulating-object mullion is removed; and 6, a dielectric layer is deposited, and a top electrode is deposited. The method for manufacturing capacitance layers can double the manufacture linewidth of the capacitance layers, solve the problem that the high technology-node capacitance layers are narrow in manufacture linewidth, and can effectively enlarge the capacitance capacity of the capacitance layers.

Description

technical field [0001] The invention relates to the field of DRAM manufacture, in particular to a method for manufacturing a capacitance layer in the DRAM. Background technique [0002] DRAM (Dynamic Random Access Memory DRAM) is a common type of memory in the consumer electronics market. At present, with the continuous improvement of the DRAM integration level, while the size of the DRAM device is reduced, the storage capacity is also continuously increased. DRAM records information through memory cells. A very widely used memory cell structure is to record information by storing and releasing charges through capacitance in the memory cell. With the improvement of DRAM integration, its production is gradually moving towards higher integrated circuit technology nodes. In the DRAM manufacturing process of this high-tech node, the manufacturing space of the capacitor layer in the X-Y direction on the plane is smaller than that of other circuit layers. [0003] For example,...

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Problems solved by technology

[0004] The purpose of the present invention is to provide a manufacturing method for a capacitor layer in DRAM, to solve the difficulties brought by the smaller line width to the manufacturing process when making a capacitor layer of a high-tech node, and to increase the capacitance of the capacitor layer at the same time

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