15 results about "Dram capacitor" patented technology

A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

Disclosed are methods and systems for depositing layers comprising a metal and nitrogen. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

The embodiment of the present application provides a hard mask pattern manufacturing method and a DRAM capacitor manufacturing method, relates to the technical field of semiconductors, and can not only avoid the influence of long-time etching of polycrystalline silicon on the pattern of an insulating film, but also avoid damaging an existing metal layer and affecting the function of the metal layer in a substrate when etching a titanium dioxide film alone. The hard mask pattern manufacturing method comprises the following steps: providing a semiconductor substrate, the substrate being provided with a layer to be etched; forming a hard mask layer on the layer to be etched, the hard mask layer comprising, from bottom to top, a polycrystalline silicon film, a titanium dioxide film and a silicon dioxide film; and performing a patterning treatment on the hard mask layer to obtain a hard mask pattern.

Provided are methods to reduce the thickness of a high-ĸ layer needed in a DRAM capacitor and, thus, allow the cell electrodes to be larger, giving higher cell capacitance. A tantalum nitride (TaN) layer is introduced as a liner in the capacitor hole before a titanium nitride (TiN) electrode layer. The TaN layer converts to a thin layer of tantalum oxide (Ta2O5), which permits a reduction in the high-ĸ layer thickness for the same capacitance versus leakage. Because this Ta2O5 is formed directly on the cell electrode, it ensures a low leakage film exists in the narrowest gaps even before the high-ĸ layer is deposited.

Disclosed are methods and systems for depositing layers comprising a metal and nitrogen. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

The present invention provides a technique for improving the etching selection ratio of a silicon nitride film with respect to a mask. The etching method includes: (a) a step of providing a substrate including a laminated film including two or more different silicon-containing films, a single-layer film containing silicon and nitrogen on the laminated film, and a mask on the single-layer film on a substrate support portion in a chamber, the mask having a side wall defining at least one opening; (b) setting the temperature of the substrate support part or the substrate to 10 DEG C or more; and (c) etching the single-layer film using plasma generated from a first processing gas containing a hydrogen fluoride gas.

The application discloses an ion beam sputtering deposition method for an integrated circuit interconnection metal layer, and belongs to the technical field of micro-nano manufacturing. In the deposition process of the metal layer, a glancing angle ion beam sputtering (IBS) physical vapor deposition (PVD) mode is adopted, so that high-quality conformal filling of metal films such as molybdenum (Mo) and ruthenium (Ru) in a tens-of-nanometer feature size (CD) and a large aspect ratio (AR) trench structure can be realized, that is, the metal films have excellent hole-filling capacity, can realize 100% sidewall coverage, and can avoid the emergence of adverse modes such as overhang and void. The application introduces the ion beam sputtering technology into the integrated circuit manufacturing process, and provides a new process solution for the deposition and filling of integrated circuit gate metal materials, middle and later interconnection pad liner / barrier / seed layer / conductive metal materials and 3D-DRAM capacitor electrode materials.

Disclosed are methods and systems for depositing layers comprising vanadium and oxygen. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

Thicker hard molds are typically required to etch deeper capacitor vias in DRAM structures. Instead of increasing hard mold thickness, hard molds can be formed with increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hard molds comprising a relatively high percentage of boron (e.g., greater than 90%) can be formed. The etch selectivity of the hard mold can be improved by performing an ion implantation process using different types of ions. Ion implantation can occur before or after the hard mold is opened using the pattern of the DRAM capacitor vias. Some designs also tilt the semiconductor substrate relative to the ion implantation process and rotate the substrate to provide greater ion penetration throughout the entire depth of the opening in the hard mold.

Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different types of ions. The ion implant may take place before or after opening the hardmask with the pattern for the DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implant process and rotate the substrate to provide greater ion penetration throughout a depth of the openings in the hardmask.

A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

Methods of forming electronic devices and film stacks comprising depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and patterned photoresist are formed, and the pattern of the patterned photoresist are transferred into the ruthenium carbide hard mask. Film stacks comprising the ruthenium carbide hard mask on the capacitor mold are also described.

An etching method includes (a) providing a substrate on a substrate support in a chamber, the substrate including a film stack including two or more different silicon-containing films, a single-layer film on the two or more different silicon-containing films, the single-layer film including silicon and nitrogen, and a mask on the single-layer film, the mask having a side wall defining an opening; (b) setting a temperature of the substrate support or the substrate to 10° C. or higher; and (c) etching the single-layer film using a plasma formed from a first processing gas, the first processing gas including a hydrogen fluoride gas.

Provided are methods to reduce the thickness of a high-κ layer needed in a DRAM capacitor and, thus, allow the cell electrodes to be larger, giving higher cell capacitance. A tantalum nitride (TaN) layer is introduced as a liner in the capacitor hole before a titanium nitride (TiN) electrode layer. The TaN layer converts to a thin layer of tantalum oxide (Ta2O5), which permits a reduction in the high-κ layer thickness for the same capacitance versus leakage. Because this Ta2O5 is formed directly on the cell electrode, it ensures a low leakage film exists in the narrowest gaps even before the high-κ layer is deposited.

A semiconductor structure is provided that includes a backside bit line connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors present on the front side of the structure.