Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics

Abstract

The invention provides a laminated dielectric layer for semiconductor devices formed by a combination of ZrO2 and a lanthanide oxide on a semiconductor substrate and methods of making the same. In certain methods, the ZrO2 is deposited by multiple cycles of reaction sequence atomic layer deposition (RS-ALD) that includes depositing a ZrI4 precursor onto the surface of the substrate in a first pulse followed by exposure to H2O / H2O2 in a second pulse, thereby forming a thin ZrO2 layer on the surface. After depositing the ZrO2 layer, the lanthanide oxide layer is deposited by electron beam evaporation. The composite laminate zirconium oxide / lanthanide oxide dielectric layer has a relatively high dielectric constant and can be formed in layers of nanometer dimensions. It is useful for a variety of semiconductor applications, particularly for DRAM gate dielectric layers and DRAM capacitors.

Description

TECHNICAL FIELD [0001] The invention relates to the field of semiconductor dielectric layers, and particularly to dielectric layers used in the formation of transistor gates and capacitors in dynamic random access memory devices. BACKGROUND OF THE INVENTION [0002] Dynamic Random Access Memory Devices (DRAMs) have become the standard type of storage device in modern computer systems. Modern DRAMs are high density, highly integrated structures having a variety of configurations, most typically stacked and trench configurations. As ever increasing density is sought, more sophisticated manufacturing processes and materials are required to achieve sub micron sized electrical component layers with reliable conformity to operational specifications. [0003] As density increases, the minimum feature sizes of DRAM components approach 100 nm and smaller. For example, the gate dielectric material thickness of MOS devices may be required to be 20 nm (200 Å) or less in certain designs. In this thi...

AI Technical Summary

Problems solved by technology

In this thickness range the most commonly used gate dielectrics, SiO2, is not suitable because of leakage current caused by direct tunneling.

There are many known high-k unilaminate dielectric materials with high dielectric constants, such as Ta2O5, TiO2 and SrTiO3, but unfortunately these materials are not thermally stable when formed directly in contact with silicon.

In addition, the interface of such materials need to be coated with a diffusion barrier, which not only adds process complexity, but also defeats the purpose of using the high-k dielectric.

Moreover, materials having too high or too low a dielectric constant may not be an adequate choice for alternate gate applications.

On the other hand, materials with relatively low dielectric constant such as Al2O3 and Y2O3 do not provide sufficient advantage over the SiO2 or Si3N4.

One striking feature of RS-ALD is the saturation of all the reaction and purging steps, which makes the growth self-limiting.

Unfortunately however, although considerable effort was put into use of ALD for growth of silicon and germanium films, difficult precursor chemistry precluded success in this area.

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