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Method and device for wafer optimized scheduling

A technology that optimizes scheduling and wafers, and is used in control/regulation systems, program control, and overall factory control to achieve high benefits, reduce production costs, and reduce computing consumption.

Active Publication Date: 2009-06-17
BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] 5. Vacuum manipulator: Transfer wafers between Load Block (loader) and Process Module (process module). The vacuum manipulator can be a double-arm manipulator, which can accommodate 2 wafers at the same time, but generally, only one wafer can be processed at a time. wafer transport

Method used

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  • Method and device for wafer optimized scheduling
  • Method and device for wafer optimized scheduling
  • Method and device for wafer optimized scheduling

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Embodiment Construction

[0048] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0049]The scheduling process flow of the present invention can run in many general-purpose or special-purpose computing system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet-type devices, multiprocessor systems, microprocessor-based systems, network PCs, distributed computing environments including any of the above systems or devices, etc.

[0050] The invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data type...

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Abstract

The invention provides a method of wafer optimal scheduling. The steps of the method comprise obtaining the quantity of wafers needed to be operated in a system and the technique sequence of each wafer, analogously calculating operating paths of a plurality of wafers according to the quantity of the wafers and the technique sequence of each wafer, wherein the path is moving sequence aggregation of each wafer in time, evaluating the operating paths of the pluralities of wafers according to the technique time efficiency of the system, taking the path with the maximum processing time efficiency of the system as the optimal path to store into a scheduling sequence, and scheduling each wafer according to paths in the scheduling sequence. The invention performs n steps simulation to all potential scheduling sequences of the system through constructing the function of the technique time efficiency of the system, and can obtain the optimal path through further analysis. Therefore, the scheme of the invention can increase the productivity of the system and reduce the manufacturing cost, thereby bringing higher benefits for manufacturers.

Description

technical field [0001] The invention relates to the technical field of process data processing, in particular to a method and device for wafer optimization scheduling in the semiconductor manufacturing industry. Background technique [0002] The best quality, the lowest manufacturing cost, quick response and flexibility are the key factors for the development of semiconductor manufacturing enterprises. [0003] The production planning and scheduling system can help semiconductor manufacturing enterprises realize these factors to a certain extent. Scheduling system is an important link to realize the optimization of production management of semiconductor manufacturing enterprises, and an indispensable part of realizing enterprise informatization. The present invention is proposed aiming at realizing wafer scheduling optimally during the wafer processing process in the semiconductor manufacturing industry. [0004] For example, in the wafer production process, an important l...

Claims

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Application Information

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IPC IPC(8): H01L21/67G06F19/00
CPCG05B19/41865H01L21/67276G05B2219/32304H01L21/67253H01L21/67763Y02P90/02
Inventor 马宝林王宝全崔琳
Owner BEIJING NAURA MICROELECTRONICS EQUIP CO LTD
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