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Conductive wire frame strip, glue sealing method and glue sealing structure

A technology of lead frame strips and lead frames, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc. It can solve the problems of wasting lead frame bar 1 space, and it is difficult to further increase the output per unit time.

Active Publication Date: 2010-09-29
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the 1:2 arrangement ratio design of the flow channel support 12 and the lead frame unit 13 has too many flow channel supports 12, which relatively limits the space that the lead frame bar 1 can be used to set the lead frame unit 13. Space, that is to say relatively limit the total number of units of the lead frame unit 13
As a result, every time the encapsulation process is performed, only a limited amount of the encapsulant 173 can be formed on the lead frame bar 1, and a lot of space of the lead frame bar 1 must be wasted, thus making it difficult to further improve the The output per unit time of the sealing procedure (units per hour, UPH)

Method used

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  • Conductive wire frame strip, glue sealing method and glue sealing structure
  • Conductive wire frame strip, glue sealing method and glue sealing structure
  • Conductive wire frame strip, glue sealing method and glue sealing structure

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Embodiment Construction

[0030] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the preferred embodiments of the present invention will be specifically cited below, together with the accompanying drawings, for a detailed description as follows:

[0031] Please refer to Figure 2A , 2B As shown in and 2C, the lead frame bar and its sealing method and sealing structure of the preferred embodiment of the present invention are mainly used in the manufacture of semiconductor packaging products with double-row lead frames, for example, in the manufacture of small outline packages (SOPs) ), Small Outline J Package (SOJ), Small Outline Transistor Package (SOT), Small Outline Wide Package (SOW), Dual Inline Package (DIP) or other similar package products.

[0032] Please refer to Figure 2A As shown, the lead frame bar 2 of the preferred embodiment of the present invention is a strip-shaped plate body, which is usually made of c...

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PUM

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Abstract

The invention discloses a lead frame strip, and a sealing method and a sealing structure thereof. The invention mainly provides the lead frame strip, which comprises at least a flow passage branch module, wherein, each flow passage branch module comprises a flow passage bracket and a plurality of lead frame units. A flow passage reserve zone is reserved on the flow passage bracket, and the flow passage reserve zone comprises a plurality of diverging point reserve zones. Each diverging point reserve zone is connected with two lead frame units from the two sides adopting two edge gate reserve zones, and further connected with another two lead frame units from the outer sides by adopting two connective gate reserve zones, to ensure that each diverging point reserve zone is connected with four lead frame units. Therefore, the lead frame strip can relatively reduce the quantity of the flow passage brackets, and simultaneously increase the quantity of the lead frame units.

Description

【Technical field】 [0001] The present invention relates to a lead frame strip and its sealing method and structure, in particular to a lead frame strip capable of increasing the output per hour (units per hour, UPH) and its sealing method and structure. Sealed construction. 【Background technique】 [0002] Nowadays, in order to meet various packaging requirements, the semiconductor packaging industry has gradually developed various types of packaging structures. Among them, silicon chips (chips) cut from semiconductor silicon wafers (wafers) are usually firstly processed by wire bonding. ) or bumping (bumping) and other appropriate methods to select and fix on the leadframe (leadframe) or substrate (substrate), and then use the encapsulation gel to encapsulate and protect the silicon chip, so that the basic structure of a semiconductor package structure can be completed. Generally, there are small outline package (small outline package, SOP), small outline J-leaded package (s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L23/31H01L21/56
CPCH01L24/97H01L2924/10253H01L2224/49171H01L2224/48247
Inventor 陈天赐陈光雄徐志宏陈焕文谢玫璘邱世杰林英士张树明陈锺国徐鸣懋
Owner ADVANCED SEMICON ENG INC
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