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Semiconductor device

A semiconductor and regional technology, applied in the direction of semiconductor devices, transistors, electrical components, etc., can solve the problems of difficult low power supply voltage drive, increase of transistor threshold voltage, and decrease of SOI layer body current, and achieve high speed and power supply voltage, low power supply voltage, effect of low threshold voltage

Inactive Publication Date: 2009-08-19
TOHOKU UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, the film thickness of the SOI layer has to be reduced, but this reduces the bulk current of the entire SOI layer, so it is necessary to set a larger difference in work function between the material of the gate electrode and the SOI layer.
As a result, the threshold voltage of the transistor increases, making it difficult to drive with a low power supply voltage

Method used

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Embodiment Construction

[0034] Next, the semiconductor device of the present invention will be described with reference to the drawings.

[0035] refer to figure 1 , shows an accumulation type (Accumulation) MOS transistor and an inversion type (Inversion) MOS transistor to which the present invention can be applied. here, figure 1 (a) and (b) represent n- and p-channel accumulation type MOS transistors (NMOS transistors and PMOS transistors), respectively, figure 1 (c) and (d) show n-channel and p-channel inversion MOS transistors, respectively.

[0036] exist figure 1In the case of the NMOS transistor shown in (a), an embedded insulating layer (BOX) is formed on the surface region of the p-type silicon substrate, and an n-type SOI (Silicon On Insulator) layer is formed on the embedded insulating layer (BOX) . Furthermore, the n-type SOI layer is formed with source, drain, and channel regions. Wherein, the source and drain regions have a higher impurity concentration than the channel region. ...

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Abstract

A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.

Description

technical field [0001] The present invention relates to semiconductor devices such as ICs and LSIs, and more particularly to an accumulation type (Accumulation) MOS transistor. Background technique [0002] As such a semiconductor device, a corresponding invention is described in Japanese Patent Application No. 2005-349857 (Patent Document 1) proposed by the present inventors. Patent Document 1 proposes that, in a semiconductor device having a circuit having at least a pair of transistors of different conductivity types, at least one of the transistors includes at least a semiconductor layer provided on an SOI substrate, a gate insulating layer covering at least part of its surface, and The gate electrode formed on the gate insulating film is formed as a normally off accumulation (Accumulation) type, and the thickness ratio of the depletion layer formed on the semiconductor layer based on the difference in work function between the gate electrode and the semiconductor layer ...

Claims

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Application Information

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IPC IPC(8): H01L29/786
CPCH01L29/78603H01L29/78648H01L29/78654H01L29/06
Inventor 大见忠弘寺本章伸程炜涛
Owner TOHOKU UNIV
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