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Package structure of integrated circuit element and manufacturing method thereof

A technology of integrated circuit and packaging structure, which is applied in the field of wafer-level packaging structure and its manufacturing, and can solve the problems of complex process and high cost

Active Publication Date: 2011-12-07
MUTUAL PAK TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The process of this known secondary packaging method is quite complicated and the cost is also very high, so a novel integrated circuit element packaging structure and its manufacturing method are needed to improve the known above-mentioned shortcomings

Method used

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  • Package structure of integrated circuit element and manufacturing method thereof
  • Package structure of integrated circuit element and manufacturing method thereof
  • Package structure of integrated circuit element and manufacturing method thereof

Examples

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Embodiment Construction

[0046] A preferred embodiment of the invention will be exemplified below with reference to the accompanying drawings. Similar elements in the attached figures are provided with the same reference numerals. It should be noted that in order to clearly present the present invention, the components in the accompanying illustrations are not drawn according to the scale of the actual object, and in order to avoid obscuring the content of the present invention, the following description also omits known components, related materials, and related processing techniques .

[0047] Figure 1 to Figure 12 It is a cross-sectional view illustrating a method for forming a package structure according to a first embodiment of the present invention. First refer to figure 1 , providing a wafer 100 . The wafer 100 has a plurality of integrated circuit elements 102 with I / O contacts 104 and a passivation layer 110 formed thereon. The integrated circuit element 102 can be a diode, such as a li...

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Abstract

The invention discloses a packaging structure of an integrated circuit element and a manufacturing method thereof. The method of the present invention comprises providing a wafer, the wafer has a plurality of integrated circuit elements; providing an extensible carrier, which has a first surface carrying the chip; forming a plurality of anti-extension layers on the extensible carrier On a second surface, the second surface is opposite to (opposite) the first surface; forming a plurality of grooves on the wafer to isolate the integrated circuit elements from each other; stretching the extendable carrier to expand the plurality of grooves; And forming an insulating layer to fill the plurality of trenches and cover the plurality of integrated circuit elements.

Description

technical field [0001] The invention relates to a packaging structure of an integrated circuit element and a manufacturing method thereof, more particularly to a chip-level packaging structure and a manufacturing method thereof. Background technique [0002] General wafer level package (wafer level package) is to directly complete the packaging structure on the chip through rewiring, dielectric material coating and solder ball process on the chip with multiple integrated circuit components. This wafer-level packaging structure is only suitable for integrated circuit components with larger dimensions and fewer output / input terminals. In detail, since the solder balls need to correspond to the contacts of the circuit board, the spacing specification usually cannot be less than 0.25mm, so for integrated circuit components that are small in size and cannot provide sufficient spacing, they cannot be applied to the general solder ball process. [0003] It is known to use secondar...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/78H01L23/31H01L23/12
Inventor 黄禄珍
Owner MUTUAL PAK TECH