Parallel frame synchronous scrambling device and descrambling device thereof

A frame synchronization and frame synchronization signal technology, applied in the direction of synchronization devices, baseband systems, digital transmission systems, etc., can solve problems such as slow computing speed, small universal range, and complex iterations, so as to improve work efficiency and processing frequency, reduce Computational complexity, the effect of less combinatorial logic

Active Publication Date: 2009-12-23
ZTE CORP
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  • Abstract
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  • Claims
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Problems solved by technology

[0009] To sum up, the disadvantages of using existing parallel scrambling/descrambling circuits are: on the one hand, for different parallel data input bit widths, it is necessary to design corresponding parallel scrambling/descrambling circuit structures, which are universal The range is small and not universal, which is not conducive to popularization and use; on the other hand, the M sequence that is not

Method used

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  • Parallel frame synchronous scrambling device and descrambling device thereof
  • Parallel frame synchronous scrambling device and descrambling device thereof
  • Parallel frame synchronous scrambling device and descrambling device thereof

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Embodiment

[0059] Combine below image 3 , only a 256-bit width SDH STM-256 signal parallel frame synchronization scrambler is described as a design example, but all solutions are applicable to parallel frame synchronization scramblers with other bit widths.

[0060] The system works at a clock frequency of 155.52MHz, and realizes the scrambling function with a parallel width of 256 bits. The M-sequence generator is composed of ROM, since the characteristic polynomial of SDH scrambling code is x 7 +x 6 +1 for using 2 7 -1 is a pseudo-random sequence with a 127-bit period, so its capacity is: (2 7 -1×256) bits, 2 7 -1 is the depth of the storage space; 256 is the width of the storage space, which contains 256 127-bit pseudo-random sequences. It should be pointed out that: image 3 Among them, M represents the entire 127-bit pseudo-random sequence, and m1, m2... represent the contents of the corresponding bit positions of the pseudo-random sequence.

[0061] image 3 Among them, th...

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Abstract

The invention relates to a parallel frame synchronous scrambling device, comprising a control unit, a memory unit and an XOR unit, wherein, the control unit is used for reading pseudo-random sequences in the memory unit in sequence and obtaining contents which correspond to parallel data in the pseudo-random sequences, the memory unit is used for storing the pre-set pseudo-random sequences and inputting the contents which correspond to the parallel data in the pseudo-random sequences into the XOR unit, and the XOR unit is used for sequentially carrying out the XOR treatment on the serially input parallel data with the contents which are obtained from the memory unit and correspond to the parallel data in the pseudo-random sequences and then outputting the scrambled data. The invention also relates to a parallel frame synchronous descrambling device, the XOR unit in the device is used for sequentially carrying out the XOR treatment on the serially input scrambled data with the contentswhich correspond to the scrambled data in the pseudo-random sequences and then outputting the obtained parallel data after the descrambling. The use of the scrambling device and the descrambling device thereof can respectively realize the scrambling and the descrambling and reduce the computational complexity.

Description

technical field [0001] The present invention relates to the realization of frame synchronization scrambling technology and descrambling technology in the communication protocol, in particular to a parallel frame synchronization scrambling device and its descrambling in synchronous digital transmission system (SDH) / optical fiber synchronous network (SONET) code device. Background technique [0002] In digital communication, the receiving end uses the 1 / 0 change on the line to recover the receiving clock of the line through a phase-locked loop to achieve bit synchronization, and transmits synchronization information through frame marks to achieve frame synchronization and then byte synchronization. Only when bit synchronization and frame synchronization are realized can the receiving end correctly extract valid user data. The user information that needs to be transmitted in the communication process is ever-changing. If the user data contains too long sequence of consecutive ...

Claims

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Application Information

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IPC IPC(8): H04J3/06H04L7/00
CPCH04L25/03866
Inventor 时立峰郭从尧
Owner ZTE CORP
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