Parallel frame synchronous scrambling device and descrambling device thereof

Abstract

The invention relates to a parallel frame synchronous scrambling device, comprising a control unit, a memory unit and an XOR unit, wherein, the control unit is used for reading pseudo-random sequences in the memory unit in sequence and obtaining contents which correspond to parallel data in the pseudo-random sequences, the memory unit is used for storing the pre-set pseudo-random sequences and inputting the contents which correspond to the parallel data in the pseudo-random sequences into the XOR unit, and the XOR unit is used for sequentially carrying out the XOR treatment on the serially input parallel data with the contents which are obtained from the memory unit and correspond to the parallel data in the pseudo-random sequences and then outputting the scrambled data. The invention also relates to a parallel frame synchronous descrambling device, the XOR unit in the device is used for sequentially carrying out the XOR treatment on the serially input scrambled data with the contentswhich correspond to the scrambled data in the pseudo-random sequences and then outputting the obtained parallel data after the descrambling. The use of the scrambling device and the descrambling device thereof can respectively realize the scrambling and the descrambling and reduce the computational complexity.

Description

technical field [0001] The present invention relates to the realization of frame synchronization scrambling technology and descrambling technology in the communication protocol, in particular to a parallel frame synchronization scrambling device and its descrambling in synchronous digital transmission system (SDH) / optical fiber synchronous network (SONET) code device. Background technique [0002] In digital communication, the receiving end uses the 1 / 0 change on the line to recover the receiving clock of the line through a phase-locked loop to achieve bit synchronization, and transmits synchronization information through frame marks to achieve frame synchronization and then byte synchronization. Only when bit synchronization and frame synchronization are realized can the receiving end correctly extract valid user data. The user information that needs to be transmitted in the communication process is ever-changing. If the user data contains too long sequence of consecutive ...

AI Technical Summary

Problems solved by technology

[0009] To sum up, the disadvantages of using existing parallel scrambling / descrambling circuits are: on the one hand, for different parallel data input bit widths, it is necessary to design corresponding parallel scrambling / descrambling circuit structures, which are universal The range is small and not universal, which is not conducive to popularization and use; on the other hand, the M sequence that is not preset needs to be used for real-time calculation with parallel data, and the larger the input bit width of parallel data, the iterations used for real-time calculation The more complicated, the computational complexity of this iterative immediate operation is high, resulting in slow operation speed, which leads to low working efficiency and processing frequency of parallel scrambling / descrambling circuits

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