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Method for reducing resource consumption of instruction memory on stream processor chip

An instruction memory, stream processor technology, applied in memory systems, concurrent instruction execution, electrical digital data processing, etc., can solve problems such as low program performance

Inactive Publication Date: 2010-01-06
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method relies too much on the capabilities of the software compiler. If the compiler predicts wrongly, the program performance will be extremely low.

Method used

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  • Method for reducing resource consumption of instruction memory on stream processor chip
  • Method for reducing resource consumption of instruction memory on stream processor chip
  • Method for reducing resource consumption of instruction memory on stream processor chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0087] figure 1 Is the overall flow chart of the present invention.

[0088] The first step is to modify the pure software-managed instruction memory in the stream processor to a software-hardware hybrid instruction memory. The software-hardware hybrid instruction memory is composed of software-managed static memory and hardware-managed cache. Such as figure 2 shown.

[0089] The second step is to add a kernel hot code search module to the compiler, and use the kernel hot code search module to search for kernel hot code. The search method flow is as follows image 3 shown.

[0090] The third step is to add instruction stream loading instructions before each kernel hot code during stream-level compilation.

[0091] The fourth step is to load the program instructions into the mixed hardware and software instruction memory, and start the program to run. The flow of the program running process and the read / write operation of the mixed hardware and software instruction memor...

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PUM

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Abstract

The invention discloses a method for reducing resource consumption of an instruction memory on a stream processor chip and aims at effectively reducing the resource consumption of the instruction memory without the addition of a complex compiling algorithm based on the prior mature hardware memory structure. The method adopts the following technical scheme: correcting the instruction memory for pure soft management in a stream processor into an instruction memory with software and hardware mixing; adding a kernel hot-code searching module in a compiler and searching kernel hot codes in the stream application according to a theorem for judging the hot codes; adding an instruction stream loading instruction before all kernel hot codes in the stream compiling; adopting a software management static memory to store the kernel hot codes so as to ensure high hit ratio, storing other instructions by adopting a cache for hardware management, and reducing the requirements of the instruction memory to memory capacity by shortening the instruction occupying time of the instruction memory, thereby the capacity of the instruction memory can be reduced. The invention can reduce the resource consumption of the instruction memory in a chip.

Description

technical field [0001] The invention relates to a method for reducing resource consumption of instruction memory in a chip, in particular to a method for reducing resource consumption of instruction memory on a stream processor chip. Background technique [0002] The stream processor based on the stream architecture is a typical representative of a new generation of intensive computing-oriented high-performance microprocessors, which are specially oriented to stream applications. Streaming applications are mainly divided into two categories: one is media applications; the other is scientific computing. Streaming applications have the following main characteristics: Computational intensity, compared with traditional desktop applications, streaming applications perform a large number of arithmetic operations on each data fetched from memory; parallelism, mainly data-level parallelism, There are both instruction-level and task-level parallelism; locality refers to the locality...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F12/08G06F12/0875
Inventor 何义张春元文梅伍楠杨乾明任巨管茂林荀长庆吴伟柴俊李京旭
Owner NAT UNIV OF DEFENSE TECH
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