High-speed high-precision flow line structure ADC

A pipeline, high-precision technology, applied in the direction of analog-to-digital converters, etc., can solve the problem of linearity, offset and other parameters affecting the gain of the circuit board, complex reference circuit and bias structure, and high circuit technology requirements.

Inactive Publication Date: 2010-01-13
胡志仁
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Problems solved by technology

Disadvantages: The reference circuit and bias structure are too complicated; the input signal needs to be specially processed to cause pipeline delay through several stages of circuits; the requirem

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  • High-speed high-precision flow line structure ADC
  • High-speed high-precision flow line structure ADC
  • High-speed high-precision flow line structure ADC

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[0019] Further describe the present invention below in conjunction with accompanying drawing.

[0020] like figure 1 The one-bit analog-to-digital conversion sub-module is composed of a comparator 1, an analog data selector 2, and a subtractor 3 with a fixed gain of 2. The positive and negative inputs of the comparator are respectively connected to the input signal V i (divisor) and reference signal D (divisor), the comparator output Q (quotient) is also used as the control terminal of the analog data selector. The input of the two-to-one analog data selector is the reference signal D and 0 level, if Q is 0, the output is 0, and if Q is 1, the output is D. The positive and negative inputs of the subtractor with a gain of 2 are respectively connected to the input signal V i Choose one of the two to simulate the output of the data selector, so that the output of the subtractor 2R is V i 2 times the remainder of division by (binary division) D.

[0021] like figure 2 Will ...

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Abstract

The invention relates to a high-speed high-precision flow line structure ADC. A circuit comprises N one-bit analog-to-digital conversion sub-modules which are connected in series step by step; each one-bit analog-to-digital conversion sub-module comprises a comparator, an alternative analog data selector and a subtracter with gain fixed at 2; the one-bit analog-to-digital conversion sub-module of each stage compares an input signal V and a reference signal D of the module, outputs a comparison result, namely the divided quotient (under binary sense) of the two signals, and outputs 2 times of the divided remainder (under binary sense) of the two signals as the input of next stage; and N conversion data are arranged according to a weight order to acquire the output of the whole analog-to-digital converter. The analog-to-digital converter is provided with a 'rounding' offset circuit which is used for improving the precision of the lowest bit. Therefore, the precision can reach 1/2 of resolution, namely LSB/2 (Vr/2<N+1>).

Description

technical field [0001] The invention relates to integrated electronic circuits, especially the field of high-speed and high-precision pipeline structure ADC manufacturing. Background technique [0002] At present, the main ADC types are parallel comparison ADC, successive comparison ADC, pipeline ADC and so on. [0003] The parallel comparison ADC inputs the analog input signal and the gradually increasing reference voltage generated by the resistor string to the input terminal of the comparator, and the n-bit resolution ADC needs 2 n -1 comparator, the output of the comparator is temperature code, which needs to be encoded into binary code or other code output. The advantage of the parallel comparison ADC is that only a single-phase clock is needed, the structure design is simple, and the high-frequency performance is good. The disadvantage is that the number of comparators required is exponentially related to the resolution, so the power consumption it consumes, the occu...

Claims

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Application Information

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IPC IPC(8): H03M1/12
Inventor 胡志仁
Owner 胡志仁
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