Systems, methods and software for preloading instructions from variable length instruction sets with appropriate predecoding

Abstract

In a processor executing instructions from a variable length instruction set, the preload instructions operate to retrieve from memory a block of data corresponding to an instruction cache line in which to execute instructions from the variable length instruction set pre-decoding, and loading the instruction and pre-decoding information into an instruction cache. The instruction execution unit indicates to the predecoder the location of the first valid instruction within the data block. The predecoder continuously determines the length of each instruction and thus determines instruction boundaries. The instruction cache line offset indicator identifying the location of the first valid instruction can be generated and provided to the predecoder in a number of ways.

Description

technical field [0001] The present invention relates generally to the field of processors, and in particular to systems, methods and software for preloading instructions from variable length instruction sets into an instruction cache and correctly predecoding the instructions. Background technique [0002] Microprocessors perform computing tasks in a wide variety of applications. Improved processor performance is almost always desired to allow faster operation and / or increased functionality through software enhancements. By taking advantage of both architectural advances (such as RISC architectures) and advances in semiconductor technology, many modern processors execute at much higher clock speeds than memory chips such as DRAM and SDRAM. To minimize the penalty of relatively slow memory accesses, these processors utilize a hierarchical memory structure in which fast on-chip cache stores data that has been recently accessed and / or that the processor expects (via software) ...

AI Technical Summary

Problems solved by technology

When an instruction is subsequently fetched from cache into the pipeline and the predecode information is determined to be wrong, the cache line must be discarded and the instruction fetched from memory again and predecoded to determine the correct instruction boundary, which is critical to processing detrimental to both performance and power consumption of the

Images