Systems, methods and software for preloading instructions from variable length instruction sets with appropriate predecoding
A pre-decoding, instruction set technology, applied in concurrent instruction execution, microprogram loading, instrumentation, etc., can solve problems such as adverse effects on processor performance and power consumption
Inactive Publication Date: 2016-10-12
QUALCOMM INC
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When an instruction is subsequently fetched from cache into the pipeline and the predecode information is determined to be wrong, the cache line must be discarded and the instruction fetched from memory again and predecoded to determine the correct instruction boundary, which is critical to processing detrimental to both performance and power consumption of the
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[0016] figure 1 A functional block diagram of processor 110 executing instructions from at least one variable length instruction set is depicted. In particular, processor 110 correctly pre-decodes instructions preloaded from a variable length instruction set. The processor 110 executes instructions in an execution unit 112 comprising a pipeline 114 including a plurality of registers or latches 116 organized in pipe levels and logic and computation circuitry such as an arithmetic logic unit (ALU) (not shown). The pipeline executes instructions according to the control logic 118 . As shown, pipeline 114 may be of a superscalar design.
[0017] A general purpose register (GPR) file 120 provides registers that form the top of the memory hierarchy. In one embodiment, the instruction execution unit also includes a status register 122, which may indicate an offset into the instruction cache line where the first instruction is located, as explained further herein. Instruction exec...
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In a processor executing instructions from a variable length instruction set, the preload instructions operate to retrieve from memory a block of data corresponding to an instruction cache line in which to execute instructions from the variable length instruction set pre-decoding, and loading the instruction and pre-decoding information into an instruction cache. The instruction execution unit indicates to the predecoder the location of the first valid instruction within the data block. The predecoder continuously determines the length of each instruction and thus determines instruction boundaries. The instruction cache line offset indicator identifying the location of the first valid instruction can be generated and provided to the predecoder in a number of ways.
Description
technical field [0001] The present invention relates generally to the field of processors, and in particular to systems, methods and software for preloading instructions from variable length instruction sets into an instruction cache and correctly predecoding the instructions. Background technique [0002] Microprocessors perform computing tasks in a wide variety of applications. Improved processor performance is almost always desired to allow faster operation and / or increased functionality through software enhancements. By taking advantage of both architectural advances (such as RISC architectures) and advances in semiconductor technology, many modern processors execute at much higher clock speeds than memory chips such as DRAM and SDRAM. To minimize the penalty of relatively slow memory accesses, these processors utilize a hierarchical memory structure in which fast on-chip cache stores data that has been recently accessed and / or that the processor expects (via software) ...
Claims
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IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/30047G06F9/30152G06F9/3802G06F9/382G06F9/30G06F9/24G06F9/38
Inventor 布莱恩·迈克尔·斯坦普尔托马斯·安德鲁·萨托里乌斯罗德尼·韦恩·史密斯
Owner QUALCOMM INC