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Semiconductor device

A semiconductor and conductive technology, applied in the direction of semiconductor devices, transistors, electric solid devices, etc., can solve the problems of poor adhesion, poor wettability, and height difference of metal sheets 131, so as to suppress poor wettability and prevent Smaller size and lower resistance effect

Inactive Publication Date: 2010-03-03
SANYO ELECTRIC CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since this height difference is also formed to be, for example, about 3 μm, a large height difference also occurs on the surface of the second emitter electrode 117 formed thereon.
Therefore, the wettability of the solder 130 applied to the surface thereof deteriorates, thereby causing a problem of poor adhesion of the metal sheet 131.

Method used

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  • Semiconductor device
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Embodiment Construction

[0065] refer to Figure 1 to Figure 5 Embodiments of the present invention will be described in detail. In this embodiment, as the semiconductor device 10 , an npn-type bipolar transistor, which is a discrete element, will be described as an example.

[0066] figure 1 It is a figure showing the structure of the semiconductor device 10 which is this Example. figure 1 is a graph representing the action region, figure 1 (A) is a floor plan, figure 1 (B) is figure 1 (A) a-a line profile, figure 1 (C) is figure 1 (A) The b-b line profile.

[0067] The semiconductor device 10 is composed of the following components: a conductive semiconductor substrate, a base region, an emitter region, a first insulating film, a base contact hole, an emitter contact hole, a first base electrode, a first emitter electrode, a first Two insulating films, a base through hole, an emitter through hole, a second emitter electrode, a second base electrode, a conductive adhesive material, and...

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Abstract

A semiconductor device. In a discrete bipolar transistor with two layers of electrode structures, the emitter electrode in a first layer and the emitter region are connected via emitter contact holesof a first insulated film formed therebetween. The emitter electrode in the second layer and the emitter electrode in the first layer are connected via emitter through holes of a second insulated filmformed therebetween. Accordingly, the emitter contact holes and the emitter through holes are overlapped under the emitter electrode in the second layer so as to generate a height difference of a thickness of two insulated films. The height difference influences the surface of the emitter electrode in the second layer, thus producing bad adhesion owing to large bump when a metal sheet is bound onthe surface with a solder. Emitter contact holes formed under the emitter electrode in the first layer and emitter through holes formed thereon are arranged so as not to overlap each other, and, foreach emitter electrode, the multiple emitter contact holes and the multiple emitter through holes are provided so as to be separated from each other. Thereby, the top surface of an emitter electrode in a second layer is influenced by at most only a height difference of each emitter through hole formed in an insulated film having a larger thickness, and thus the flatness of the top surface of the emitter electrode in the second layer is improved. Accordingly, fixation failure of a metal sheet can be avoided.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of flattening transistor electrodes, expanding a safe operating region, avoiding heat dissipation, and reducing resistance components. Background technique [0002] As a discrete bipolar transistor, there is known a bipolar transistor in which two layers of base electrodes and emitters are respectively arranged on an operating region composed of a lattice-shaped emitter region and an island-shaped base region. Electrodes (for example, refer to Patent Document 1). [0003] refer to Figure 6 , taking an npn transistor as an example to illustrate an existing semiconductor device. [0004] Figure 6 (A) is a plan view of the whole semiconductor device 100, Figure 6 (B) is Figure 6 (A) j-j line profile, Figure 6 (C) is Figure 6 (A) K-k line profile. In addition, in Figure 6 In (A), the second-layer electrodes are indicated by dotted line...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/73H01L29/417
CPCH01L29/66295H01L29/732H01L29/0692H01L29/0804H01L29/41708H01L2224/40245H01L24/40H01L2224/0603H01L2224/29339H01L2224/32245H01L2224/37147H01L2224/45144H01L2224/48247H01L2224/48465H01L2224/73265H01L24/37H01L2224/84801H01L2224/8485H01L2924/00014H01L2224/73221H01L2924/00
Inventor 高桥和也
Owner SANYO ELECTRIC CO LTD
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