Multi-core timer implementing method and system

A technology of a multi-core system and an implementation method, which is applied in the field of computer multi-core, can solve the problems that the second half cannot be scheduled in time, the timer processing is not timely, and the timer timeout is not supported, and the conditions for improving polling efficiency and deployment are achieved. Easy, avoid the effect of inaccurate timer

Inactive Publication Date: 2010-06-02
BEIJING LEADSEC TECH
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Problems solved by technology

For dedicated processors that are separated from the operating system, based on polling, and have no process concept support, this method cannot be implemented.
[0015] 3) When there are many hard interrupts in the system, because the priority of the hard interrupt is higher than that of the lower half bottom, the lower half bottom cannot be scheduled in time, so that the timer processing is not timely, and the timer deviates
[0016] 4) The implementation of the current timer is based on 32-bit jiffies. For a system with a system clock interrupt frequency of 1000Hz, the 32-bit jiffies counter overflows in only 49.7 days
Therefore, this timer mechanism does not support timer timeouts exceeding 49.7 days

Method used

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  • Multi-core timer implementing method and system

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Embodiment Construction

[0041] The present invention provides a multi-core timer implementation scheme for a multi-core system. Unlike the existing Linux timer mechanism, which relies on operating system interrupts and lower half bottoms, the present invention selects a core from multiple cores as the timer processing core, which is determined by The core uses the multi-core system timing function to execute the scheduling and adjustment of the multi-core timer vector, which gets rid of the dependence on the operating system interrupt and the lower half bottom, and reduces the kernel overhead.

[0042] see figure 1 , which is a flow chart of the multi-core timer implementation method of the present invention, including:

[0043] S101: Randomly select a core from the multi-core system as a timer processing core;

[0044] S102: The timer processing core checks the time through the time mechanism of the multi-core system;

[0045] S103: The timer processing core executes the scheduling and adjustment ...

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Abstract

The invention discloses multi-core timer implementing method and system, wherein the method comprises the following steps of: selecting a core as a timer processing core at will from the multi-core system, wherein the timer processing core checks the time through a time mechanism of the multi-core system; and executing the dispatch and the adjustment on multi-core timer vectors by the timer processing core at intervals of preset time. The multi-core timer implementing method and system can separate from an operating system, support massive data and not influence the system performance and has higher precision.

Description

technical field [0001] The invention relates to the field of computer multi-core technology, in particular to a method and system for realizing a multi-core timer. Background technique [0002] Since the creation of the first microprocessor in 1971, computer experts have been constantly exploring the work efficiency of a single-chip CPU. Until the beginning of the 21st century, the work efficiency of a single-chip CPU has been increased to the physical theoretical limit of the material. The improvement of single-chip CPU efficiency has reached a limit. However, with the popularization of computer technology, the contradiction between people's increasing computing needs and the limited working efficiency of a single-chip CPU has become increasingly prominent. In this case, various computer technologies have slowed down the pace of development due to the bottleneck of CPU efficiency. How to break through the physical theoretical efficiency limit of a single-chip CPU has beco...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48
Inventor 何志福
Owner BEIJING LEADSEC TECH
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