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Test structure and test method for precisely evaluating reliability performance of gate oxide

A reliable, gate oxide technology, used in semiconductor/solid-state device testing/measurement, electrical components, electrical solid-state devices, etc., can solve problems such as process development limitations, and achieve the effect of accurately evaluating reliable performance

Active Publication Date: 2012-08-01
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the limitation of parallel diodes, it is impossible to carry out accurate quantitative analysis tests for evaluating interface state defects, mobile ions, etc., which greatly restricts the development of the process.

Method used

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  • Test structure and test method for precisely evaluating reliability performance of gate oxide
  • Test structure and test method for precisely evaluating reliability performance of gate oxide
  • Test structure and test method for precisely evaluating reliability performance of gate oxide

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0024] The test structure for accurately evaluating the reliability performance of gate oxide in the present invention includes a MOS structure, and a polysilicon fuse 10 is connected in parallel on the gate oxide layer of the MOS structure.

[0025] Because the plasma in the process is the main cause of gate oxide layer damage, the present invention is connected with a fusible polysilicon fuse 10 in parallel on the gate oxide layer, and the polysilicon fuse 10 can be used in processes such as manufacturing before the test. The plasma is directed onto the silicon substrate to protect the gate oxide layer of the test object, and a fresh gate oxide film of the front-end process can be obtained.

[0026] The gate oxide layer of the present invention may be composed of a transistor (MOSFET) with a small area, or may be a large area of ​​different types of gate oxide capacitors. When the polysilicon fuse 10 is connected to the transistor, the transistor gate oxide characteristics a...

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PUM

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Abstract

The invention discloses a test structure for precisely evaluating reliability performance of gate oxide. The test structure comprises an MOS structure, wherein a gate oxide layer of the MOS structure is connected in parallel with a polysilicon fuse; and the MOS structure is an N-type transistor, a P-type transistor or a gate oxide capacitor. The gate oxide layer is connected in parallel with the fusible polysilicon fuse; before testing, the polysilicon fuse conducts out plasma, static electricity and other possible damage in the process flow; in the testing process, the testing structure fuses the polysilicon fuse, can perform relevant quantitative testing analysis on a charge pump, a CV and the like in terms of interface state disadvantages, mobile ions and the like, and can precisely evaluate the reliability performance of the gate oxide layer. The invention also discloses a testing method for precisely evaluating the reliability performance of the gate oxide.

Description

technical field [0001] The invention relates to an integrated circuit test structure, in particular to a test structure for accurately evaluating the reliability performance of gate oxide, and also relates to a test method for accurately evaluating the reliability performance of gate oxide. Background technique [0002] With the rapid improvement of transistor integration in Ultra Large Scale Integration (ULSI), the reliability of gate oxide has gradually become one of the most important issues. The reliable characteristics of gate oxide directly affect key parameters such as gate leakage, saturation / linear current threshold voltage, and transconductance during transistor use. The interface states and defects of the gate oxide layer will affect the long-term use of the device. Therefore, it is highly desirable to accurately test and evaluate this aspect of transistors. [0003] In the traditional test method, in the process of precise quantitative analysis of interface sta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/66
CPCH01L2924/0002
Inventor 刘玉伟张会锐卜皎曹刚
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP