Method for compressing built-off self-test data of system-on-a-chip and special decoding unit thereof

Abstract

The invention relates to an integrated circuit testing technology, in particular to a method for compressing test data in built-off self-test (BOST) method for a system-on-a-chip and a special decoding unit thereof. By embedding an entire test set into different inversion sequences, the purpose of compressing the data can be achieved only by storing the seeds of the inversion sequences; the inversion rule for the inversion sequences can be different, so as to improve the compression flexibility. The invention also provides a special decoding unit for realizing the method for compressing the built-off self-test data of the system-on-a-chip. The special decoding unit comprises a counter, a decoder or a gate for spreading the number of the inversion sequences, a configurable network for controlling the inversion position from the seeds to generation of the test vector, and a D trigger with output feedback.

Description

【Technical field】 [0001] The invention relates to integrated circuit testing technology, in particular to a test data compression method and a dedicated decoding unit in a built-off self-test (Built-Off Self-Test, BOST) method for a System-on-a-Chip (SoC) . 【Background technique】 [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in one chip, and can integrate pre-designed and verified IP, such as memory, microprocessor, DSP, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system-on-chip or system-on-a-chip. SoC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market, but the testing of SoC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be...

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macroscopic mechanical devices.

[0004] 2. Automatic test equipment (ATE for short) is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more IP integrated in the SoC, the greater the amount of test data required

Runlength-based encoding methods include: Golomb codes, FDR codes, EFDR codes, alternate codes, alternate continuous codes and other encoding methods, but these methods all have problems such as complex control protocols; statistics-based encoding methods include: choose Huffman Encoding, variable-length Huffman encoding, but these methods have problems such as high decompression hardware overhead and complicated decoding process; dictionary-based encoding methods include: LZ77, LZ78, LZW, etc., but these methods require large dictionary storage overhead, and at the same time Large number of variable-length indexes complicates decoding

The method based on the fold counter can embed the entire test set into multiple fold sets, so that the storage of the entire test set becomes the storage of multiple fold seeds, which is a very good method. Uniformity, so that the number of test vectors that can be embedded in a single fold set is very small, and the number of fold sets needed in the end is still large; another disadvantage of the fold set is that the restoration from the fold seed to the fold vector is serial , so its application time is very long, which increases the testing process

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