Memory circuits and routing of conductive layers thereof

Abstract

A memory circuit includes at least one memory cell for storing a datum. The memory cell is coupled with a word line, a bit line, a bit line bar, a first voltage line, and a second voltage line. The memory circuit includes a first conductive layer, a second conductive layer coupled with the first conductive layer, a third conductive layer coupled with the second conductive layer. The third conductive layer is routed for the word line and is free from including the bit line, the bit line bar, the first voltage line, and the second voltage line within the memory cell.

Description

technical field [0001] The present invention relates to semiconductor circuits, and more particularly to the wiring of memory circuits and their conductive layers. Background technique [0002] Memory circuits have been implemented in various applications. Memory circuits may include dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory circuits. The SRAM circuit includes a plurality of memory cells (cells). For a 6-T static memory that provides an array of memory cells, each of the memory cells contains six transistors. The 6-T SRAM memory cell is coupled to a bit line BL, an inverted bit line BLB and a word line WL. Four of the six transistors form two sets of interleaved-coupled inverters for storing data representing "0" or "1". The remaining two transistors are used as access transistors to control the access of data stored in the memory cell. [0003] The 6-T SRAM memory cell, as mentioned above, is also coupled to the po...

AI Technical Summary

Problems solved by technology

High length / width ratio results in narrow wordline routing

A narrow wordline increases the resistance of the wordline, adversely affecting the RC time delay of signals passing through the wordline coupled to 128, 256 or more memory cells

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