Chip resetting method, chip and double rate memory system

Abstract

The invention discloses a chip resetting method, the chip and a double rate memory system. The method comprises the following steps of: receiving an input signal to generate a reset signal; executing reset operation on a function module except a physical layer of a double rate memory controller in the chip, and generating a reset control signal according to the reset signal and an indicating signal written by a processor; and executing the reset operation on the physical layer of the double rate memory controller according to the reset control signal. The embodiment of the invention can well avoid the problem of off-chip DDR device suspension in a hard reset state, can only improve hardware, do not require interaction of software and hardware in resetting, avoid interaction risk of the software and the hardware, improve the stability of the chip, avoid long-term response of soft reset, and shorten resetting time.

Description

technical field [0001] The invention relates to the field of electronics, in particular to a chip reset method, a chip and a double-speed memory system. Background technique [0002] DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory) referred to as double rate memory or DDR device, DDR SDRAM is developed from SDRAM (Synchronous Dynamic Random Access Memory, synchronous dynamic random access memory), Data can be transmitted once on the rising edge and falling edge of the clock, and its transmission rate is fast, the capacity is large, and the price is cheap, which can well meet the needs of a large amount of data cache. DDR SDRAM is mainly used for high-speed and large-capacity storage of data. The double-rate memory system is composed of DDR SDRAM and a chip that accesses DDR SDRAM. The chip is mainly composed of DDRC (DDR Controller, double data rate controller), DDR PHY (DDR PhysicalLayer, doubl...

AI Technical Summary

Problems solved by technology

[0005] In the research and practice of the prior art, the inventors of the present invention have found that in the chip reset method of the prior art, software intervention is required to solve the deadlock problem caused by reset, and a soft reset must be performed before the hard reset, which increases the The complexity of the operation, the response time of the soft reset is long, and the reset is not timely enough, which increases the risk of software and hardware interaction

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