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Array substrate and manufacturing method thereof

An array substrate and substrate technology, applied in the field of liquid crystal displays, can solve problems such as signal delay, and achieve the effect of reducing the time length of signal delay

Inactive Publication Date: 2012-05-23
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of realizing the use of the above-mentioned array substrate, the inventors found at least the following problems: Since there are many data scanning lines and gate scanning lines arranged on the TFT array substrate, and the data scanning lines and gate scanning lines are crossed, Large parasitic capacitances will be formed at the intersections of scan lines and gate scan lines, as well as the gate and source / drain of thin film transistors, which will cause delays in the signals input to the data scan lines

Method used

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  • Array substrate and manufacturing method thereof
  • Array substrate and manufacturing method thereof
  • Array substrate and manufacturing method thereof

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Embodiment 1

[0049] An embodiment of the present invention provides an array substrate, such as image 3 and Figure 4As shown, the array substrate includes a substrate 270, and gate scanning lines 220 and data scanning lines 210 arranged to cross each other on the substrate 270, and pixel electrodes arranged at each intersection of the gate scanning lines 220 and data scanning lines 210 230 and thin film transistor 250. Figure 4 The middle table shows the cross-sectional view of the thin film transistor 250 and the cross-sectional view of the intersection of the gate scan line 220 and the data scan line 210 . Figure 4 The thin film transistor 250 shown in includes a gate electrode 251 connected to the gate scanning line 220, a source electrode 252 connected to the data scanning line 210, a drain electrode 253 connected to the pixel electrode 230, and a gate electrode 253 overlapping with the gate scanning line 220 and Define the semiconductor layer 257a of the channel 254 between the ...

Embodiment 2

[0058] An embodiment of the present invention also provides a method for manufacturing an array substrate, the following refers to Figure 5 to Figure 10 The manufacturing method is described.

[0059] First, if Figure 5 A gate metal layer is deposited on a substrate 270 as shown. Subsequently, the gate metal layer is etched through a mask patterning process to form a gate pattern, the gate pattern includes a gate scan line 220 and a gate 251, wherein the gate 251 is integrated with its adjacent gate scan line 220 and connect together.

[0060] A gate insulating film 280 is deposited on a substrate 270 having a gate pattern using a deposition technique (see Image 6 ). And on the gate insulating film 280, a semiconductor layer (the material is amorphous silicon) and a doped semiconductor layer (the material is n+ amorphous silicon) are sequentially formed; the semiconductor layer is shown in 257a in the figure, and the doped semiconductor layer is shown in the figure 257...

Embodiment 3

[0070] An embodiment of the present invention provides an array substrate, such as Figure 11 and Figure 12 As shown, the array substrate includes a substrate 370, and gate scanning lines 320 and data scanning lines 310 arranged to cross each other on the substrate 370, and pixel electrodes arranged at each intersection of the gate scanning lines 320 and data scanning lines 310 330 and thin film transistor 350. Figure 12 , except for the cross-sectional view of the thin film transistor 350 and the cross-sectional view of the intersection of the gate scan line 320 and the data scan line 310 . Figure 12 The thin film transistor 350 shown in includes a gate electrode 351 connected to the gate scanning line 320, a source electrode 352 connected to the data scanning line 310, a drain electrode 353 connected to the pixel electrode 330, and a gate electrode 353 overlapping with the gate scanning line 320 and Define the semiconductor layer 356a of the channel 354 between the sour...

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Abstract

The invention discloses an array substrate and a manufacturing method thereof, relates to the technical field of liquid crystal displays, and solves the problem of overlarge parasitic capacitance between a data scanning line and a grid scanning line in the prior art and prevention of electrostatic breakdown. In the array substrate of the embodiment of the invention, a gas layer is arranged between a grid electrode and a source / drain electrode of a thin film transistor, and a gas layer positioned between the grid scanning line and the data scanning line is arranged at the intersection of the grid scanning line and the data scanning line. The embodiment of the invention is mainly used for the field of the liquid crystal displays, particularly for the array substrates needing small parasiticcapacitance between the data scanning line and the grid scanning line.

Description

technical field [0001] The invention relates to the technical field of liquid crystal displays, in particular to an array substrate and a manufacturing method thereof. Background technique [0002] like figure 1 and figure 2 As shown, the TFT array substrate includes a gate scanning line 1 and a data scanning line 2 arranged on the lower substrate to cross each other, and a TFT 7 and a pixel electrode 9 are arranged in each area formed by the intersection of the gate scanning line 1 and the data scanning line 2 and the common electrode line 16. For the specific structure of TFT7, see figure 2 The TFT sectional view shown, the TFT7 includes a gate 3 connected to the gate scanning line 1, a source 4 connected to the data scanning line 2, and a drain 5 connected to the pixel electrode 9, wherein the drain 5 passes through the contact hole 8 is connected to the pixel electrode 9, and a channel 6 is provided between the source 4 and the drain 5. The TFT 7 also includes a s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G02F1/1368H01L27/12H01L21/77H01L21/84
Inventor 郝昭慧董敏张弥
Owner BOE TECH GRP CO LTD