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NOR flash memory and word line driver circuit thereof

A word line driver, driver circuit technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as being difficult to be practical

Active Publication Date: 2014-11-05
CONVERSANT INTPROP MANAGEMENT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the hierarchical (hierarchical) column decoding method described in U.S. Patent No. 6,515,911 has several advantages, it also takes up a lot of attention area, so it is difficult to be called practical.

Method used

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  • NOR flash memory and word line driver circuit thereof
  • NOR flash memory and word line driver circuit thereof
  • NOR flash memory and word line driver circuit thereof

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Embodiment Construction

[0029] The word line driver circuit is used to boost the voltage of the selected word line to a target voltage, and also provide final decoding of the address of the selected cell, and each word line is accompanied by a word line driver circuit. With the improvement of the layout and process technology, the cell pitch in the memory array is arranged to be narrower, and when the word lines are getting closer, the size of the word line driver circuit can also be reduced accordingly. The design of the wordline driver of the present invention reduces its size by limiting the number of operating elements in the wordline driver, and the bias states disclosed in the present invention are an example of the operational capabilities of the wordline driver of the present invention.

[0030] Figure 8 It is a comparison diagram of a parallel flash memory cell array and a serial flash memory cell array, as shown in the figure: In a parallel flash memory cell array, each segment does not sh...

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Abstract

The invention discloses a word line driver of an NOR flash memory, which is coupled with a memory array, wherein the memory array is provided with a plurality of memory units forming multiple sections, and each section is provided with a main word line combined with a plurality of local word lines; the local word lines are coupled with the main word lines respectively through a local word line drive circuit mainly consisting of a first MOS (Metal Oxide Semiconductor) transistor and a second MOS transistor; the first MOS transistors are coupled between corresponding main word lines and the local word lines; and the second MOS transistors are coupled between corresponding local word lines and a first bias voltage end.

Description

[0001] This application is a divisional application of an invention patent application with an application date of March 13, 2007, an application number of 200710086331.1, and an invention title of "word line driver for OR non-flash memory". technical field [0002] The invention relates to a semiconductor memory, in particular to an improved design of a word line driver of a flash memory. Background technique [0003] The memory array structure most widely used in semiconductor integrated circuits and non-volatile memories is the NOR (or not) type. In this type of structure, the gate terminals of the memory cells in the same column are connected in common, the drain terminals of the memory cells in the same row are connected in common, and the source terminals are shared by all the cells in a segment. figure 1 Discloses the conventional NOR array diagram described in U.S. Patent Publication No. 6515911. The location of each memory cell is determined by a selected row and a ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/02G11C16/08
Inventor 陈宗仁郭忠山林扬杰
Owner CONVERSANT INTPROP MANAGEMENT INC