Self-timing writing tracking type static random access memory

Abstract

The invention relates to a self-timing writing tracking type static random access memory. The self-timing writing tracking type static random access memory comprises an analog total word line driver, an analog writing driver and a total word line driving array, wherein the output end of the analog total word line driver transmits a signal to the analog writing driver through an analog total word line by adopting a U-shaped structure; the output of the analog writing driver is connected to a bit line tracking array; and the bit line tracking array is connected with a general control circuit through a programmable accelerating writing circuit and a writing tracking reset circuit. The invention designs the self-timing writing tracking type static random access memory without an additional return path. The self-timing writing tracking type static random access memory has the advantages that: due to the adoption of a plurality of memory tracking units, the resistance of the self-timing writing tracking time sequence against the change caused by process deviation can be improved; the tracking of a writing control signal can be implemented better by using an analog load integrated in thedirections of the word line and the bit line; and the flexibility of the design and the test can be improved due to the adjustability of the analog writing driver and a accelerating writing tracking circuit. The self-timing writing tracking type static random access memory can also be applied to a compiler of the static random access memory.

Description

Technical field: [0001] The invention relates to a high-performance memory, in particular to a self-timing write tracking type static random access memory. Background technique: [0002] With the continuous improvement of the CMOS process level and the continuous reduction of the minimum feature size, the process deviation becomes larger and the delay of the sequential circuit increases. If this change cannot be fully considered, it is very likely to cause timing disorder and functional failure of the circuit in some cases. [0003] In recent years, with the large and extensive application of embedded static random access memory (SRAM), its performance is directly related to the performance of the system-on-chip (SOC) where it resides. In order to save the chip area, the storage unit of SRAM usually adopts smaller design size and geometric design rules, which will lead to greater variation of its process deviation, which in turn will lead to greater variation of its memory ...

AI Technical Summary

Problems solved by technology

This patent also uses only one memory tracking unit as the write timing control, and there is also a long path for the write tracking return signal. These shortcomings will have a negative impact on the design of high-performance SRAM

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