Programmable decimal frequency divider

Abstract

The invention discloses a programmable decimal frequency divider which comprises a frequency divider, an asynchronous counter and a control logic circuit, wherein the frequency divider is used for selecting a frequency division working mode 1 or a frequency division working mode 1.5 according to mode selection signals; the asynchronous counter is formed by connecting a plurality of 2 or 3 dividing units in series and is used for generating different frequency division number N according to control signals (P0, P1...,Pn-1) of each 2 or 3 dividing unit, wherein n and N are integers; and the control logic circuit is used for receiving output signals of each of the 2 or 3 dividing units connected in series of the asynchronous counter and mod signals to generate mode selection signals for controlling the work of the frequency divider, so that the (N+0.5) frequency division mode of the frequency divider is half of a clock period longer than that of the N frequency division mode of the frequency divider in a complete output signal period. In the programmable decimal frequency divider provided by the invention, the (N+0.5) frequency division mode is half of a clock period longer than that of the N frequency division mode in a complete output signal period; and the programmable decimal frequency divider not only can be used for carrying out N frequency division and (N+0.5) frequency division but also can be used for carrying out programmable setting on the N value.

Description

technical field

[0001] The present invention relates to a programmable fractional frequency divider, especially a programmable N or (N+0.5) frequency divider suitable for phase-locked loops. Background technique

[0002] Phase Locked Loop (Phase Locked Loop) is widely used in many fields such as digital communication system, wireless communication system, digital circuit system and disk drive system, and its application specifically includes noise and jitter suppression, time delay effect suppression, frequency Synthesizers, clock recovery and carrier extraction, modulation and demodulation, etc.

[0003] The traditional phase-locked loop structure such as figure 1 As shown, it is a feedback system composed of a phase frequency detector 101 , a charge pump 102 , a loop filter 103 , a voltage controlled oscillator 104 and a frequency divider 105 . It uses an external crystal oscillator to provide a reference signal, the on-chip voltage-controlled oscillator 104 generates an...

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