Programmable decimal frequency divider

A technology of fractional frequency divider and frequency divider, which is applied in the direction of pulse counter, counting chain pulse counter, pulse technology, etc., can solve the problem of insufficient triggering and driving ability of input clock, and achieve the effect of low phase noise and low quantization error

Active Publication Date: 2010-12-08
SOI MICRO CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, all D flip-flops, D latches, and one-of-two selectors in this structure are directly driven by the input clock. When the frequency division number N is large, the trigger driving capability of the input clock may be insufficient.

Method used

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  • Programmable decimal frequency divider
  • Programmable decimal frequency divider
  • Programmable decimal frequency divider

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0085] Embodiment one: Figure 7 The shown programmable fractional frequency divider is mainly composed of three parts: a frequency divider 70 for frequency division by 1 or 1.5, a control logic circuit 71 and an asynchronous counter 72 .

[0086] The structure of the frequency divider 70 with 1 or 1.5 frequency division is similar to the traditional 2 or 3 frequency divider structure, except that the single-edge D flip-flop is replaced by the current double-edge trigger D flip-flop (701, 702). Double-edge triggered D flip-flops (701, 702) can be used as Figure 10 or as Figure 11 structures shown (but not limited to Figure 10 with Figure 11 structure), including two D latches (triggered by high and low levels respectively) and a selector for choosing between two. In addition to double-edge-triggered D flip-flops ( 701 , 702 ), the frequency divider 70 for frequency division by 1 or 1.5 also includes an OR gate 703 and a NAND gate 704 . When the mode selection signal ...

Embodiment 2

[0093] Embodiment two: Figure 8 The shown programmable fractional frequency divider is mainly composed of four parts: a frequency divider 70 for dividing by 1 or 1.5, a control logic circuit 71 , an asynchronous counter 72 and a selection logic circuit 80 .

[0094]The selection logic circuit 80 includes OR gates 801, 802, 803, etc., and one-of-two selectors 804, 805, 806, etc. The control logic circuit 71 receives the output signals of each OR gate of the selection logic circuit 80 and the mod signal, and performs a NAND operation on them. When the output of one of the OR gates is low level or mod is low level, the mode selection signal is high level, and the frequency divider 70 of 1 frequency division or 1.5 frequency division operates in 1 frequency division mode; when each or The outputs of the gates are all at high level, and when mod is at high level, the mode selection signal is at low level, and the frequency divider 70 with 1 or 1.5 frequency division works in the ...

Embodiment 3

[0102] Embodiment three: Figure 9 The shown programmable fractional frequency divider is mainly composed of four parts: a frequency divider 70 for frequency division by 1 or 1.5, a control logic circuit 71 , an asynchronous counter 90 and a selection logic circuit 80 . Among them, the asynchronous counter 90 includes D flip-flops 901, 902, 903, etc., and the inverting output end of each D flip-flop is connected to its own input end, except that the first-stage D flip-flop 901 is divided by 1 or 1.5 The output of frequency divider 70 is used as the driving clock, and the driving clocks of the other D flip-flops are all provided by the output of the two-to-one selector at the previous stage. Each D flip-flop realizes the function of frequency division by 2. The selection control circuit 80 according to the selection control signal S 1 , S 2 ,...,S n It is decided to "shield" the number of D flip-flops in the asynchronous counter 90, so that the frequency division number N c...

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Abstract

The invention discloses a programmable decimal frequency divider which comprises a frequency divider, an asynchronous counter and a control logic circuit, wherein the frequency divider is used for selecting a frequency division working mode 1 or a frequency division working mode 1.5 according to mode selection signals; the asynchronous counter is formed by connecting a plurality of 2 or 3 dividing units in series and is used for generating different frequency division number N according to control signals (P0, P1...,Pn-1) of each 2 or 3 dividing unit, wherein n and N are integers; and the control logic circuit is used for receiving output signals of each of the 2 or 3 dividing units connected in series of the asynchronous counter and mod signals to generate mode selection signals for controlling the work of the frequency divider, so that the (N+0.5) frequency division mode of the frequency divider is half of a clock period longer than that of the N frequency division mode of the frequency divider in a complete output signal period. In the programmable decimal frequency divider provided by the invention, the (N+0.5) frequency division mode is half of a clock period longer than that of the N frequency division mode in a complete output signal period; and the programmable decimal frequency divider not only can be used for carrying out N frequency division and (N+0.5) frequency division but also can be used for carrying out programmable setting on the N value.

Description

technical field [0001] The present invention relates to a programmable fractional frequency divider, especially a programmable N or (N+0.5) frequency divider suitable for phase-locked loops. Background technique [0002] Phase Locked Loop (Phase Locked Loop) is widely used in many fields such as digital communication system, wireless communication system, digital circuit system and disk drive system, and its application specifically includes noise and jitter suppression, time delay effect suppression, frequency Synthesizers, clock recovery and carrier extraction, modulation and demodulation, etc. [0003] The traditional phase-locked loop structure such as figure 1 As shown, it is a feedback system composed of a phase frequency detector 101 , a charge pump 102 , a loop filter 103 , a voltage controlled oscillator 104 and a frequency divider 105 . It uses an external crystal oscillator to provide a reference signal, the on-chip voltage-controlled oscillator 104 generates an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/66H03K23/68
Inventor 王小松黄水龙张海英
Owner SOI MICRO CO LTD
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