Semiconductor memory apparatus and data write method of the same

Abstract

A Semiconductor memory apparatus includes: a data latch driving unit configured to latch and drive data and to transfer the driven data via a first data bus, based on a detection start signal and a detection stop signal; a data masking latch driving unit configured to latch and drive a data masking signal and to transfer the driven data masking signal via a second data bus, based on the detection start signal and the detection stop signal; an error detection unit configured to perform an error detection operation on the data and the data masking signal to generate an error detection signal, based on the detection start signal and the detection stop signal; an error detection driving unit configured to drive the error detection signal and to transfer the driven error detection signal via a third data bus; a write control unit configured to generate a write control signal based on the data masking signal transferred via the second data bus and the error detection signal transferred via the third data bus; and a data write unit configured to write aligned data transferred via the first data bus into a core circuit, based on the write control signal.

Description

[0001] Cross References to Related Applications [0002] Pursuant to 35 U.S.C §119(a), this application claims priority to Korean Application No. 10-2009-0059869 filed Jul. 1, 2009, the entire contents of which are hereby incorporated by reference as if fully set forth. technical field [0003] Various embodiments of the present invention relate generally to semiconductor memory devices, and in particular to data writing circuits for semiconductor memory devices. Background technique [0004] A semiconductor storage device usually serially receives / outputs multi-bit data from / to an external storage control device. On the other hand, a semiconductor memory device has a plurality of internal global data buses (GIOs) for receiving / outputting multi-bit data from / to a core area, and the multi-bit data transferred via the global data buses is parallel data. In this way, since multi-bit data is transmitted in parallel within the semiconductor storage device, and the multi-bit data...

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Problems solved by technology

However, when defective bits are included in the data mask signal DM as described above, input data bits that should not be written into the core circuit, such as DIN, have already been input (ie, written) into the core circuit, which makes Difficult to repair data write operations

[0010] Thus, a typical semiconductor memory device cannot effectively prevent the above-mentioned malfunction in a data write operation when an error bit occurs in a data mask signal.

In addition, since semiconductor memory devices operate at high speeds, the possibility of occurrence of the above-mentioned failures is high

However, typical semiconductor memory devices do not have the necessary reliability for data write operations

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