Anti-radiation EEPROM memory array structure

A storage array, radiation-resistant technology, applied in electrical components, electric solid-state devices, circuits, etc., can solve the problem that the EEPROM memory cell array structure does not have application value, etc., and achieve the effect of improving radiation resistance.
CN101982882BActive Publication Date: 2011-10-2658TH RES INST OF CETC
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Patents(China)
Current Assignee / Owner
58TH RES INST OF CETC
Publication Date
2011-10-26

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Abstract

The invention discloses an anti-radiation EEPROM memory cell array structure. The design eliminates the influence of the total ionizing dose (TID) generated by radiation to the field current leakage between adjacent memory cells in the EEPROM memory array. The invention comprises the following parts: (1) the HVNMOS technology is used for isolating adjacent EEPROM memory cells; and (2) the grid end of a pipe for isolating is connected with -2V voltage. The total dose resistance capability of the array design reaches more than 300kRad (Si), and a current leakage passage does not exist between adjacent cells after isolating. The anti-radiation capability is enhanced, and simultaneously, the memory property of the memory cell array is not influenced.
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Description

technical field

[0001] The invention relates to a design method of a radiation-resistant EEPROM storage array. It belongs to the technical field of integrated circuits. Background technique

[0002] As a non-volatile storage device, EEPROM is widely used in the field of aviation and aerospace. However, due to the complexity of the space application environment, storage arrays are often affected by radiation, resulting in key data loss or device failure. How to meet the needs of space applications and improve the radiation resistance of EEPROM has been a research hotspot for many years.

[0003] In the prior art, no additional isolation structure is added between memory cells formed by NMOS transistors, and the cells are isolated by field oxygen in the process. Such as figure 1 As shown, 2 is the active region, 3 is the gate oxide layer, 4 is the gate, and 1 is the field oxygen region between the left and right NMOS transistors. In a normal environment, there is no condu...

Claims

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