Array substrate and manufacturing method thereof
A technology for array substrates and substrate substrates, which is applied in semiconductor/solid-state device manufacturing, optics, instruments, etc., can solve problems such as poor display, increased common voltage of common electrodes, and uneven common voltage, so as to improve display quality and increase Stability, the effect of avoiding public voltage rise
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Embodiment 1
[0026] figure 1 It is a partial top view structural schematic diagram of the array substrate provided by Embodiment 1 of the present invention. The array substrate includes a base substrate 1 on which data lines 2 and gate scanning lines 3 intersecting horizontally and vertically are formed. The data lines 2 and the gate scanning lines 3 surround a plurality of pixel units arranged in a matrix form, figure 1 Shown in is a schematic top view structural diagram of some pixel units, the area where each pixel unit is located is the display area, and the part outside the display area is the edge area.
[0027] Each pixel unit is provided with a first TFT switch and a pixel electrode 4 . The first TFT switch specifically includes a first gate electrode 6 , a first active layer 7 , a first source electrode 8 and a first drain electrode 9 . The first gate electrode 6 is formed in the same layer as the gate scanning line 3 and connected to each other. The first source electrode 8 a...
Embodiment 2
[0044] Figure 4 It is a partial top view structural schematic diagram of the array substrate provided by Embodiment 2 of the present invention. This embodiment can be based on Embodiment 1. Further, a jumper 10 is provided on the array substrate, and the jumper 10 is connected to the common electrode line 5 in adjacent pixel units; the common electrode line 5 is connected to the discharge electrode through the jumper 10. structure. The non-directly connected common electrode lines 5 on the array substrate can be connected to each other by setting jumper wires 10 , thereby increasing the connection points between the common electrode lines 5 and making the common voltage in the common electrode lines 5 in the entire array substrate more uniform.
[0045] The position of the jumper 10 depends on the position of the common electrode line 5 . In this embodiment, the common electrode lines 5 are formed on the same layer as the gate scanning lines 3 and are parallel to the gate s...
Embodiment 3
[0055] Figure 5 It is a flowchart of a method for manufacturing an array substrate provided in Embodiment 3 of the present invention, and the method specifically includes the following steps:
[0056] Step 501, depositing a gate metal thin film on the base substrate 1;
[0057] Step 502, use a monotone mask to pattern the gate metal film to form a gate scanning line 3, a first gate electrode 6, a common electrode line 5, a light blocking strip 24, a first terminal 171 of a capacitor and a second The pattern of the gate electrode 13, the gate scanning line 3, the first gate electrode 6, the common electrode line 5 and the light shielding bar 24 are formed in the display area, and the first terminal 171 of the capacitor and the second gate electrode 13 are formed between the display area in the outer edge region;
[0058] In the pattern formed in step 502, the first gate electrode 6 is connected to the gate scanning line 3, the common electrode line 5 is integrally formed wit...
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