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Semiconductor chip, seal ring structure and manufacturing method thereof

A semiconductor and sealing ring technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of large chip area, low utilization rate of semiconductor chip 1 area, occupation, etc., to achieve effective improvement The effect of the use of the area

Inactive Publication Date: 2011-05-04
FORTUNE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In terms of design, the corners of the semiconductor chip 1 usually need to lay out the calibration marks 12 and the sealing ring 14 at the same time, which will occupy too much chip area, resulting in low area utilization of the semiconductor chip 1

Method used

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  • Semiconductor chip, seal ring structure and manufacturing method thereof
  • Semiconductor chip, seal ring structure and manufacturing method thereof
  • Semiconductor chip, seal ring structure and manufacturing method thereof

Examples

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Embodiment Construction

[0050] refer to image 3 , image 3 It is a top view of an embodiment of the semiconductor chip of the present invention. like image 3 As shown, the semiconductor chip 2 includes an integrated circuit area 20 , at least one chip corner marking area 22 and a sealing ring 24 . Wherein, the chip corner marking area 22 adjacent to the integrated circuit area 20 is a non-circuit area. The sealing ring 24 is disposed outside the integrated circuit area 20 and surrounds the integrated circuit area 20 , and forms a calibration mark Mark in the chip corner marking area 22 .

[0051] Cooperate image 3 , refer to Figure 4 . Figure 4 for image 3 A cross-sectional view of the present invention shows a part of the structural cross-sectional view of the sealing ring. like Figure 4 As shown, the sealing ring 24 of the present invention includes a marking sealing ring structure A and a buffer sealing ring structure B, wherein the marking sealing ring structure A is arranged with...

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PUM

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Abstract

The invention relates to a semiconductor chip which comprises an integrated circuit region, at least one chip corner mark region and a seal ring structure, wherein the chip corner mark regions are adjacent to the integrated circuit region; the seal ring is arranged at the outer side of the integrated circuit region and surrounds the integrated circuit region; and a correction mark is formed on the chip corner mark regions. The invention discloses a manufacturing method of the seal ring arranged in the semiconductor chip. The semiconductor chip can achieve the purposes of identifying and aligning without an extra correction mark and can improve the use of the effective area of the semiconductor chip.

Description

technical field [0001] The invention relates to a semiconductor chip, a sealing ring structure and a manufacturing method thereof, in particular to a semiconductor chip and a sealing ring structure using the sealing ring as a calibration target and a manufacturing method thereof. Background technique [0002] refer to figure 1 , is a top view of a conventional semiconductor chip. A conventional semiconductor chip 1 includes an integrated circuit region 10 , a calibration mark 12 arranged at the corner of the semiconductor chip 1 and a sealing ring 14 arranged at the periphery of the semiconductor chip 1 . Wherein, the integrated circuit region 10 may include various electronic devices, such as passive devices and active devices formed on a substrate. At the same time, the calibration mark 12 is an alignment mark, such as an optical alignment mark, an electron microscope mark or other alignment marks, and the calibration mark 12 is used as a calibration machine (not marked)...

Claims

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Application Information

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IPC IPC(8): H01L27/02H01L23/00H01L23/544H01L23/485H01L21/02H01L21/60
CPCH01L23/544H01L2223/54426H01L2223/54453H01L2223/5446H01L2924/0002H01L2924/00
Inventor 陈国强陈宴毅
Owner FORTUNE SEMICON